View ISPLSI6192SM-70LM_7966636.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 isplsi 6192 high density programmable logic with dedicated memory and register/counter modules features a family of highly integrated, cell-based, programmable logic devices consisting of: memory module register/counter module programmable logic module 159 user logic/memory/register/counter pins 25000-gate overall density memory module options fifo (6192ff), single-port ram (6192sm) or dual- port ram (6192dm) programmable organizations: ?single 256 x 18 or 512 x 9 ?dual 128 x 18 or 256 x 9 (6192sm) 31 dedicated data and control interface pins programmable almost empty and almost full flags (fifo) dedicated arbitration/busy logic (dual-port ram) register/counter module 8 cascadable 16-bit functions 9 programmable modes including counter, timer, shift register and register options 24 dedicated module data and control pins includ- ing terminal count flags automatic preload, count up/down options high density programmable logic module 8000-gate general purpose programmable logic block 192 general purpose logic registers 24-input, twin generic logic blocks (glbs) imple- ment any registered or combinatorial functions high-speed global interconnects 96 i/o pins with input registers security cell prevents unauthorized design copy- ing high performance e 2 cmos technology f max = 77 mhz maximum operating frequency t pd = 15 ns propagation delay f cnt = 125 mhz counter frequency 50mhz fifo data rate 20ns memory access time electrically erasable and reprogrammable unused product term shutdown saves power in-system programmable ?supports isp or ispjtag programming change logic and interconnects in seconds reprogram soldered devices for debugging ieee 1149.1 boundary scan compatible table 1. isplsi 6192 device features s n o i t p o e l u d o m y r o m e m r e t n u o c / r e t s i g e r e l u d o m e l b a m m a r g o r p l a r e n e g e l u d o m c i g o l s n o i t c n u f o f i f f f 2 9 1 6 t r o p - e l g n i s m a r s m s 2 9 1 6 t r o p - l a u d m a r s m d 2 9 1 6 e l b a m m a r g o r p r e m i t / r e t n u o c / r e t s i g e r r e t s i g e r t f i h s / r o d e r e t s i g e r : l a s r e v i n u l a i r o t a n i b m o c n o i t a z i n a g r o ) e l b a m m a r g o r p ( 8 1 x 6 5 2 r o 9 x 2 1 5 : e l g n i s ) y l n o m s 2 9 1 6 ( 9 x 6 5 2 r o 8 1 x 8 2 1 : l a u d t i b 6 1 x 8 e l b a e d a c s a c s d r o w s l l e c o r c a m 2 9 1 e c a f r e t n i l a n r e t x e s n i p l o r t n o c 3 1 & o / i 8 1s n i p l o r t n o c 8 & o / i 6 1 / s k c o l c 5 / o / i 6 9 s e l b a n e t u p t u o l a b o l g 2 e c n a m r o f r e p ) c c a t ( e m i t s s e c c a y r o m e m s n 0 2 r e t n u o c z h m 5 2 1 ) t n c f ( y c n e u q e r f ) d p t ( y a l e d c i g o l s n 5 1 ) x a m f ( y c n e u q e r f z h m 7 7 y t i l i b a m m a r g o r p e l b a m m a r g o r p m e t s y s - n i y t i l i b a t s e t t s e t n a c s y r a d n u o b 1 . 9 4 1 1 e e e i e g a k c a p ) p f q m ( k c a p t a l f d a u q l a t e m n i p - 8 0 2 copyright ?1999 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. may 1999 tel. (503) 681-0118; 1-800-lattice; fax (503) 681-3037; http://www.latticesemi.com functional block diagram register/counter module memory module options: ?fifo (6192ff) ?single port ram (6192sm) ?dual port ram (6192dm) programmable logic module 6192_05
specifications isplsi 6192 2 functional block diagram figure 1. isplsi 6192 functional block diagram output routing pool (orp) global routing pool (grp) f3 f2 f1 f0 register/ counter module goe0 goe1 toe isp and boundary scan tap reset i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 i/o 50 i/o 51 i/o 52 i/o 53 i/o 54 i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 i/o 95 i/o 94 i/o 93 i/o 92 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 output routing pool (orp) e3 e2 e1 e0 output routing pool (orp) c0 c1 c2 c3 output routing pool (orp) d0 d1 d2 d3 b0 b1 b2 b3 a0 a1 a2 a3 output routing pool (orp) output routing pool (orp) input bus input bus input bus note: since certain signal names are duplicated on memory module and register/counter module pins ( oe , dio), the notation: oe (ram) oe (rc) dio (ram) dio (fifo) dio (rc) will be used periodically in this data sheet to differentiate signals. refer to table on module i/o cell connectivity regarding the use of module i/o cells as inputs to the global routing pool. input bus input bus twin generic logic blocks (glbs) input bus bscan/ispen tdi/sdi tdo/sdo tck/sclk tms/mode trst isplsi 6192sm single port sram 6192 block.2.eps memory module enable serial out (sout) serial in (sin) dio 15 oe tc/co 3 tc/co 2 tc/co 1 tc/co 0 dio 14 dio 13 dio 12 dio 11 dio 10 dio 9 dio 8 dio 7 dio 6 dio 5 dio 4 dio 3 dio 2 dio 1 dio 0 a4 a5 a6 a7 a0 a1 a2 a3 a8/rwh rwl cs oe dio 0 dio 1 dio 2 dio 3 dio 4 dio 5 dio 6 dio 7 dio 8 dio 9 dio 10 dio 11 dio 12 dio 13 dio 14 dio 15 dio 16 dio 17 isplsi 6192dm dual port sram a4 a5 a6 a7 a0 a1 a2 a3 a8/rwh rwl cs oe busya dio 0 dio 1 dio 2 dio 3 dio 4 dio 5 dio 6 dio 7 dio 8 dio 9 dio 10 dio 11 dio 12 dio 13 dio 14 dio 15 dio 16 dio 17 isplsi 6192ff fifo alf rst ef ff ale rd or wr oe dio 0 dio 1 dio 2 dio 3 dio 4 dio 5 dio 6 dio 7 dio 8 dio 9 dio 10 dio 11 dio 12 dio 13 dio 14 dio 15 dio 16 dio 17 clk 1 clk 0 clk 2 ioclk 1 ioclk 0 y0 y1 y2 y3 y4 megablock
specifications isplsi 6192 3 the isplsi 6192 device is a high density, cell-based programmable logic devices that contain a dedicated memory module, a dedicated register/counter module and an 8000-gate general-purpose programmable logic block. output routing pools (orp) and a global routing pool (grp) give complete interconnectivity between these elements. the cell-based architecture with dedi- cated modules have been added to enhance the functionality, performance and utilization of the devices. the isplsi 6192 family is offered in three versions: the 6192ff (fifo), 6192sm (single port ram) and 6192dm (dual port ram). all three devices employ the same general-purpose programmable logic module and regis- ter/counter module, with only the memory module functionality changing. the pinouts of the three devices are different only in the memory module control interface pins. memory module lattice semiconductor offers a dedicated dual-port fifo module in the 6192ff device. the fifo is user configurable as a 256 x 18 or 512 x 9 block and is connected to the external world through dedicated fifo i/o pins. the other data port of the fifo goes to the grp. a variety of fifo control flags such as full ( ff ), almost full ( alf ), almost empty ( ale ) and empty ( ef ) are available as dedicated device outputs. these signals are also available as inputs to the grp to facilitate use by on- chip logic. the fifo operation is discussed at length in the following sections. the 6192sm features a single-port memory module. the module can be organized either as a single 256 x 18 or 512 x 9 single port memory or as two smaller 128 x 18 or 256 x 9 single port memories. the external interface features memory address input pins (a0-a8), read/ write (rwl, rwh), chip select ( cs ), output enable ( oe ) control lines, and 18 bidirectional data lines. the memory can be accessed from this external interface or from the internal grp based on the user's design. the 6192dm has functionality similar to the 6192sm, but access from the grp or external pins is supported concurrently. dedicated arbitration logic and busy flags help to resolve issues arising from simultaneous access description from both ports of the same memory location. the busy signal from the external port ( busya ) is available at a dedicated device pin. the dual-port memory is configurable as a single 256 x 18 or 512 x 9 memory. register/counter module an additional feature of the 6192 devices is a dedicated register/counter module. eight 16-bit blocks are avail- able to function as registers or shift registers. in addition, four of these blocks can be programmed to operate as loadable up/down counters. these four blocks include carry-in and carry-out connections to allow counter cas- cading up to 64 bits. the register/counter block also has a 16-bit data port connected to the grp along with a variety of control inputs and status flag outputs. programmable logic module the basic unit of general-purpose programmable logic on the 6192 devices is the twin generic logic block (twin glb). there are a total of 24 of these twin glbs in the 6192 devices. each twin glb has 24 inputs, a programmable and array and two or/exclusive-or arrays as well as eight outputs which can be configured independently to be combinatorial or registered. all twin glb logic inputs come from the grp. four twin glbs, 16 i/o cells and one orp form a logic megablock. the 16 i/o cells within a megablock share one product term output enable and two global output enable signals. the outputs of four twin glbs are connected to a set of 16 i/o cells by the orp. the isplsi 6192 device contains six of these megablocks. the grp has, as its inputs, the outputs from all of the twin glbs and all of the inputs from the bidirectional i/o cells as well as independent bidirectional data bus ports from the fifo and register/counter blocks. flag outputs from these modules as well as control inputs are also connected to the grp. all these signals are made avail- able to the inputs of the twin glbs. delays through the grp have been equalized to minimize timing skew and logic glitching. all glb outputs are brought back into the grp so that they can be connected to the inputs of any other logic
specifications isplsi 6192 4 block on the device. the device has 96 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, a latched input, an output or a bidirectional i/o pin with 3- state control. output signal levels are ttl compatible and the output drivers can source 4ma and sink 8 ma. each output can be programmed independently for fast or slow output slew rate to minimize overall output switch- ing noise. the devices are packaged in space saving 208-pin metal quad flat pack (mqfp) packages. clocks in the isplsi 6192 device are provided through five dedicated clock pins. the five pins provide three clocks to the twin glbs and two clocks to the i/o cells. in-system programmability the isplsi 6192 devices features 5-volt in-system pro- grammability and in-system diagnostic capabilities. through this capability, the devices offer non-volatile on-the-fly reprogrammability of logic and memory to support truly reconfigurable systems. boundary scan the 6192 families also have boundary scan capability, consisting of dedicated cells connected between the on- chip system logic and the device s input and the output pins. all i/o pins have associated boundary scan regis- ters, with 3-state i/o using three boundary scan registers and inputs using one. the device supports all ieee 1149.1 mandatory instructions, which include bypass, extest and sample.
specifications isplsi 6192 5 figure 2. isplsi 6192 twin glb general purpose programmable logic module the and array consists of two sets of 20 product terms which are the logical product of any of the 24 twin glb inputs. these inputs all come from the grp, and are either feedback signals from any of the 24 twin glbs, inputs from the external i/o cells or outputs from the memory or register/counter modules. all twin glb input signals are available to the product terms in both the logical true and complemented forms which makes bool- ean logic reduction easier. the two product term sharing arrays (ptsa) take the 20 product terms each and allocate them to two groups of four twin glb outputs. there are four or gates, with four, four, five and seven product term inputs respec- tively. the output of any of these or gates can be routed to any of the four twin glb outputs, and if more product the following is a brief description of the general purpose programmable logic module. for additional information on this module see the 1000/e family architectural description in the lattice semiconductor data book or cd-rom. generic logic block the twin glb is the standard logic block of the lattice semiconductor isplsi 6192 family. this twin glb has 24 inputs, eight outputs and the logic necessary to implement most standard logic functions. the internal logic of the twin glb is divided into four separate sections: the and array, product term sharing array, reconfigurable registers, and control section. and array 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 inputs from global routing pool 18 19 20 21 22 23 control functions twin glb 0130/6192 pt output enable to output enable mux pt reset global reset mux clk 0 clk 1 clk 2 pt clock mux o0 o1 o2 o3 to global routing pool and output routing pool m u x m u x m u x m u x product term sharing array d registers 3 4 4 7 d q d q d q d q 14 15 16 17 18 19 13 12 11 10 9 8 7 5 4 3 2 1 0 6 3 + 4 (shared) pt's and xor 7 + 4 (shared) pt's 4 pt bypass single pt o0 o1 o2 o3 to global routing pool and output routing pool m u x m u x m u x m u x control functions pt output enable to output enable mux reconfigurable registers d, j - k, and t 4 4 5 7 d q d q d q d q product term sharing array 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pt reset global reset mux clk 0 clk 1 clk 2 pt clock mux
specifications isplsi 6192 6 figure 4. isplsi 6192 family global clock structure terms are needed, the ptsa can combine them as necessary. if the user s main concern is speed, the ptsa can use a bypass circuit with four product terms to increase the performance of the cell. this can be done to any or all of the eight outputs of the twin glb. the reconfigurable registers consist of four d-type flip- flops with an xor gate on the input. the xor gate in the glb can be used either as a logic element or to reconfigure the d-type flip-flop to emulate a j-k or t-type flip-flop. this greatly simplifies the design of counters, compara- tors and alu type functions. the registers can be bypassed if the user needs a combinatorial output. each register output is brought back into the global routing pool and is also brought to the i/o cells via the output routing pool. reconfigurable registers are not available when the four product term bypass is used. figure 2 illustrates the mixed mode configurations of the twin glb. various signals which control the operation of the glb outputs are driven from the control functions. the clock for the registers can come from any of three clk0-2 inputs or from a product term within the glb. the reset signal for the glb can come from the global reset pin ( reset ) or from a product term within the block. the global reset pin is always connected and is logically "ored" with the pt reset (if used). an active reset signal always sets the q of the registers to the logic 0 state. the output enable for the i/o cells associated with the glb comes form a product term within the block. use of a product term for output enable makes it unavailable for use as a general-purpose logic term. megablock structure four twin glbs, 16 i/o cells and one orp make up a megablock. each twin glb has a maximum fan-in of 24 inputs, and no dedicated inputs associated with any megablock. each twin glb has eight associated out- puts. a total of 32 glb outputs are fed to the orp. however, only 16 out of the 32 outputs feed to 16 i/o cells. the megablock structure is shown in figure 3. clk 0 clk 1 clk 2 ioclk 1 ioclk 0 y0 y1 y2 y3 y4 0163a/6192 figure 3. isplsi 6192 family megablock block diagram output routing pool glb a0 glb a2 glb a1 glb a3 i/o cell 0 i/o cell 1 i/o cell 2 i/o cell 3 i/o cell 4 i/o cell 5 i/o cell 6 i/o cell 7 i/o cell 8 i/o cell 9 i/o cell 10 i/o cell 11 i/o cell 12 i/o cell 13 i/o cell 14 i/o cell 15 0028a/3256
specifications isplsi 6192 7 global clock structure the global clock structure is made up of five global clock input pins, y0, y1, y2, y3, and y4. this is shown in figure 4. three of the clock pins are dedicated for glb clocks and the remaining two clock pins are dedicated for i/o register clocks. all input clock signals are fed directly to the glb clock input via a clock multiplexer. the glb global clocks do not have inversion capability, but the product term clock does have inversion capability before it reaches the clock multiplexer. output enable controls a global test oe signal (toe) is hardwired to all i/o cells and is useful to perform static testing of all the 3-state output buffers within the device. in addition to the test oe signal, two global oes (goe0 and goe1) are connected to all i/o pins. the product term oe is shared between two megablocks resulting in twice the glbs being able to use a single oe signal. the megablock oe signal and global oe signals are fed to an oe multiplexer. the oe signals, with the exception of the test oe, have inversion capability after going through the oe multiplexer as shown in figure 5. figure 5. isplsi 6192 family output enable controls mux portion of i/o cell 0 i/o pin mux portion of i/o cell 1 i/o pin mux portion of i/o cell 31 i/o pin mux portion of i/o cell 30 i/o pin 8:1 mux twin glb a1 twin glb a0 twin glb a3 twin glb a2 oe controls.3k intro ptoea ptoeb ptoea ptoeb ptoea ptoeb ptoea ptoeb megablock mux goe0 goe1 to other i/o cells toe mux mux mux to other i/o cells ptoes from any other megablock
specifications isplsi 6192 8 figure 6. boundary scan block diagram boundary scan boundary scan (ieee 1149.1 compatible) is a test fea- ture incorporated within the device to provide on-chip test capabilities during pcb testing. five input signal pins, bscan, tdi, tck, tms, trst , and one output signal pin, tdo, are associated with the boundary scan logic cells. these signals share the same dedicated signal pins used for isp programming. the signal bscan is associated with the ispen pin, tdi corresponds to the sdi pin, tck corresponds to the sclk pin, tms corre- sponds to the mode pin, and tdo corresponds to the sdo pin. when ispen is asserted low, the mode, sdi, sdo, and sclk options become active for isp program- ming. otherwise, bscan, tdi, tck, tms, tdo, and trst options become active for boundary scan testing of the device. the boundary scan block diagram is shown in figure 6. tdi is the test data serial input, tck is the boundary scan clock associated with the serial shift register, tms is the test mode select input, tdo is the test data output, and finally trst is the reset signal pin. the user interfaces to the boundary scan circuitry through the test access port (tap). the tap consists of a control state machine, instruction decoder and instruc- tion register. the tap is controlled using the test control lines: test data in (tdi), test data out (tdo), test mode select (tms), test reset ( trst ) and test clock (tck). the tap controls the operation of the boundary scan registers after decoding the instruction code sent to the instruction register (see table 3). the boundary scan registers for the i/o cells are shown in figure 7. as illustrated in the figure, each general- purpose i/o cell contains 3 registers, 2 latches and 5 multiplexers to implement the ability to capture the state of the i/o cell or set the state of the output path of the cell or function as a conventional i/o cell. module i/o cells eliminate the output enable registers (oe control comes from oe pins). the boundary scan registers required for an input only cell are shown in figure 8. an input only cell can only have its state captured, which only requires one mux and one register. output-only cells are shown in figure 9. here, two registers control the output and output enable. all of the input, output and i/o cells are serially connected together in a long chain. the scan out of one cell is connected to the scan in of the next cell. the cells are connected in the following order: tdi to i/o47 through i/o32, y4, y3, y2, y1, reset , toe, goe1, goe0, y0, i/o31 through i/o0, busya , a0/ rst (fifo), a1/ ef , a2/ ff , a3/ ale , a4/ alf , a6, a7, a8/rwh, rwl/ rd or wr , cs , oe (ram), di/o0 through di/o17(ram or fifo), di/o0 through di/o15(rc), oe (rc), sin, sout, en- able, tc/co0 through tc/co3, i/o48 through i/o95, to tdo. note that input-only pins add only one register to control the inputs to the boundary scan chain (a0, a5, a6, a7, a8, rwl, cs , sin, enable, y0-y4, reset , toe, goe0, goe1). output-only pins add two registers to the chain ( busya , sout, tc/c0-3) to control the output and output enable. pins that function as input or output add three registers to the chain (i/o0-95, a1/ ef , a2/ ff , a3/ ale , a4/ alf ) to control inputs, outputs and enables. di/o0-17(ram or fifo) and di/o0-15(rc) add two registers to the chain per pin for input/output control (output enable for these pins is generated from the respective oe pin register. oe (rc) adds two registers to control its input and the output enable for di/o0-15(rc). oe (ram) adds three registers: one to control its input and two to control the output enables for the high and low bytes of the di/o(ram) pins. test data output (tdo) to i/o, input or output cell boundary scan registers test data input (tdi) test mode select (tms) boundary scan enable (bscan) boundary scan clk (tck) reset signal ( trst ) 0846 boundary scan
specifications isplsi 6192 9 figure 7. boundary scan registers for i/o cells dq i/o pin m u x dq dq dq dq m u x m u x m u x m u x i/o in scan out (to next pad) scan in (from previous pad) shift dr clock dr update dr glb oe glb output extest 0847 figure 9. boundary scan registers for output-only cell output pin m u x dq dq dq dq m u x m u x m u x scan out (to next pad) scan in (from previous pad) shift dr clock dr update dr glb oe glb output extest 0847b figure 8. boundary scan registers for an input only cell input m u x dq scan out (to next pad) scan in (from previous pad) shift dr clock dr 0848
specifications isplsi 6192 10 table 2. boundary scan timing specifications v cc symbol table 2 - 0028aisp-3k/6 k t rst t h t su t co parameter supply voltage reset time from valid v hold time setup time clock to output condition min. typ. max. units 4.75 100 10 60 5.0 5.25 60 v s ns ns ns cc t clkh t clkl clock pulse duration, high clock pulse duration, low 60 60 ns ns t ispe ispen / bscan to tdo 1 s figure 10. boundary scan waveforms vcc bscan valid tms tdi tclk tdo t su t h t clkh t clkl t rst t h t ispe valid* t co 0181d/3256a don t care t su driven by tdo * in shift ir/dr states table 3. boundary scan instruction codes instruction name bypass note: lsb shifts in first. extest sample/ preload code 11111 00000 11100 bypasses registers of selected device(s) drives external i/o with bscan registers loads and shifts data into bscan registers description table 10- 0007
specifications isplsi 6192 11 figure 11 illustrates the functionality of the fifo. data in, write ( wr ), read ( rd ) and reset ( rst ) form the inputs and data out, full ( ff ), almost full ( alf ), almost empty ( ale ) and empty ( ef ) constitute the outputs of the fifo module. when wr is active, data can be written into the ram array sequentially, independent of read. when rd is active, data can be read from the ram array sequen- tially, again, independent of write. the dedicated module reset or global reset pin of the device can be used to reset the internal address pointers to the first location of ram array, and all the flags to an empty state. the fifo signals the empty and full condition by asserting the empty and full flags, respectively. the almost empty and almost full flags can be used to set the interrupt request in advance. read, write and reset inputs into the fifo also have user-programmable polarity control so these normally active low signals can be individually defined as active high or active low. the fifo is user configurable and can be configured as: description ports used 256 x 18 fifo a to b 256 x 18 fifo b to a 512 x 9 fifo a to b 512 x 9 fifo b to a integration of high-speed static ram technology with dedicated internal support logic yields a high-perfor- mance, high-density fifo memory module on the isplsi 6192ff. a fifo is a first-in/first-out buffer that acts as an elastic buffer between two synchronous or asynchro- nous systems with simultaneous read/write accesses. the data rate between the two systems can be regulated by monitoring the status flags and throttling the read and write accesses. because data is produced and accepted at different rates, it is important to monitor the boundary conditions (full or empty) of the data buffer. failure to act on the boundary conditions will result in data overflow or under- flow. the empty and full flags can also be fed back internally to inhibit further read and write operations until the fifo is no longer empty or full. while offering the basic features of a fifo, the dedicated fifo module in the 6192ff device also provides two new user-programmable flags: almost-empty and almost- full. these flags can be used as early warning flags in critical real-time applications such as data acquisition, high-speed data link and pipeline digital signal process- ing applications. in a multi-tasking environment, the almost-empty and almost-full flags can also be used to set the interrupt request in advance, so that the cpu has sufficient time to perform the switching task. fifo description (6192ff) figure 11. fifo module functional block diagram read control and pointer ram array 256 x 18 512 x 9 write control and pointer wr flag logic reset logic 18/9 data in a or b (0-17/0-8) 18/9 full almost full empty almost empty rst global reset ( reset ) rd data out a or b (0-17/0-8) port a only oe
specifications isplsi 6192 12 fifo operation the fifo can be configured in two directions: port a to b, where data flows from the dedicated fifo i/o pins to the grp, and port b to a, where data flows from grp to i/o pins. accesses between ports can be asynchronous. the module utilizes an 18- or 9-bit wide data bus to make it user configurable as a 256 x 18 or 512 x 9 block. a write cycle is initiated on the falling edge of the write ( wr ) provided the full flag ( ff ) is not set. data is stored in the ram array sequentially and independently of any ongoing read operation. when the fifo is full, the full flag goes low (becomes active), and further write opera- tions are inhibited to prevent data overflow, i.e., the external write ( wr ) is blocked internally from going low. upon the completion of a valid read operation, the full flag will go high allowing a valid write to begin. if the fifo is not read after a reset, the full flag will go low after 256 (256 x 18) or 512 (512 x 9) writes. the almost full flag ( alf ) is programmable via e 2 cmos cells on the device. it can be programmed to go low at any given location. it does not, however, inhibit further write operations. the almost full location must be above the almost empty flag location. a read cycle is initiated on the falling edge of read ( rd ) if the empty flag ( ef ) is not set. the data is accessed from the ram array sequentially, independent of any ongoing write operations. after read goes high, the data outputs (data out 0-17) will return to a high impedance condition until the next read operation. when all the data has been read from the fifo, the empty flag ( ef ) will go low, allowing the final read cycle but inhibiting the further read operations. the data outputs will remain in a high impedance state while the fifo is empty. when the fifo is empty, the internal read pointer is blocked from going low. once a valid write operation has been accom- plished, the empty flag will go high and a valid read can then begin. the almost empty flag can be programmed to go low at any given point but does not inhibit further read operations. this location has to be below the almost full flag location. figure 12. full flag from last write timing waveform ff write ( wr ) last write ignored write first write first read additional reads additional writes read ( rd ) t wff t rff t wpf figure 13. empty flag from last read timing waveform ef read ( rd ) last read ignored read first read first write additional writes additional reads write ( wr ) data out 0-17 t ref t dv t a t wef valid valid t rpe
specifications isplsi 6192 13 reset is accomplished whenever the fifo reset ( rst ) input is taken to a low state. during reset, internal read and write pointers are set to the first location of the fifo memory array. almost full and full flags are cleared (high), and almost empty and empty flags are set (low). a reset is required after power up before a write operation can take place. figure 14. almost-empty/almost-full flag timing waveform figure 16. fifo reset timing waveform alf ale write ( wr ) read ( rd ) t waf t wae t rae t raf (7/8 full) (1/8 full) almost empty (1/8 full - 1) almost full (7/8 full + 1) almost empty (1/8 full - 1) read ( rd ) ef , ale write ( wr ) rst alf , ff t rsc t rs t rss t rsr t rss t alel, t efl t alfh, t ffh figure 15. asynchronous write and read operation timing waveform data in 0-17 write ( wr ) read ( rd ) data out 0-17 data out valid data out valid data in valid data in valid t rlz t a t rc t rr t rpw t dv t rhz t wc t wpw t wr t ds t dh
specifications isplsi 6192 14 fifo interfaces port a to b configuration figure 17 below shows the port a to b configuration of the fifo. port a is connected to the i/o cells and port b to the grp of the device. i/o cells (port a) are used to write data into the fifo when the write signal goes low. the grp (port b) is driven with the data from the fifo when the read signal goes low. the status of the various control flags is passed to the i/o cells and grp. in the 512 x 9 fifo configuration, the high-order 9 bits (data in a9-17) are used for writing in data. the remain- ing data i/o pins are pulled high. port b to a configuration figure 18 below shows the port b to a configuration of the fifo. the grp inputs (port b) provide data to the fifo when the write signal goes low. i/o cells read data from the fifo when the read signal goes low. the i/o cells are in the high impedance state when the read signal is high. the status of various control flags is passed to the i/o cells and grp. when not used for memory interfacing, the dio 0-17 (fifo) and ale and alf pins may be used for general- pupose logic inputs into the grp. figure 17. port a to b configuration figure 18. port b to a configuration fifo 256 x 18 512 x 9 global routing pool di/o (0-17/0-8) rd or wr i/o cells rst wr reset rd data in a data out b port b port a ff alf ale ef full almost full almost empty empty 18/9 18/9 fifo 256 x 18 512 x 9 global routing pool rd reset wr data out a data in b port b port a full almost full almost empty empty 18/9 18/9 di/o (0-17/0-8) rd or wr i/o cells rst ff alf ale ef oe
specifications isplsi 6192 15 operation. cs is the chip select line. there is a separate cs for each port. the cs line has to be active in order to perform a read/write operation on the memory module. all the input signals, control as well as the data lines, are user selectable to be active high or low. the dual port ram has a default configuration of active low for the cs . when not used for memory interfacing, the dio 0-8 (ram) and a3-a7 pins may be used for general-purpose logic inputs into the grp. the dual port ram is user configurable and can be configured as any of the following: description ports used 256 x 18 dual port ram a & b 256 x 18 dual port ram a & b w/byte write (9 bit write) 512 x 9 dual port ram a & b port a interfaces with the external world through dio pins and port b is internal to the device via the grp. a dual port static ram constitutes the memory module in the isplsi 6192dm device. the dual port ram is organized as a 512 x 9 memory module with a parity bit added to each byte of data. the memory module can be accessed for read or write concurrently via two separate ports as long as both ports do not access the same memory location at the same time. figure 19 illustrates the functionality of the dual port ram. it can be sub-divided into 3 parts: memory array, address decoders and the control and arbitration logic. the 18-bit data bus is bidirectional and can be used to read data from the memory array or write data to the memory array. a byte read/write operation involves 8-bits of data and a parity bit. 8 address bits (addr 0-7) are used to access a particular word location in memory array. rwh is associated with the higher 9 data bits and rwl is used for lower 9 data bits. there are 2 rwh and 2 rwl lines, one pair for each port. these are inputs to the control logic to select the type of operation to be performed. depending on the configuration. it can be a word read/write operation, or byte read and/or write dual port ram module description (6192dm) figure 19. dual port ram functional block diagram ram array 256 x 18 512 x 9 18/9 data in b (from grp 0-17/0-8) data out b (to grp 0-17/0-8) oe address decode address b (addrb0 - 7) address decode address a (addra0 - 7) arbitration and control logic rwhb busy b (to grp) rwlb cs b rwha busy a (to pin) rwla cs a dio 0-17 (port a)
specifications isplsi 6192 16 dual port ram configurations 256 x 18 dual port ram figure 20 below shows the 256 x 18 and 512 x 9 configurations of the dual port ram. addra 0-7 form the 8-bit address bus used to access one of the 256 locations from port a which is connected to the external pins. addrb 0-7 form the 8-bit address bus used to access one of the 256 locations from port b which is connected to the grp. rwla is the control line which determines the type of operation to be performed with the 18-bit data bus from the dio pins. a high rwla signal reads 18-bits of data from the memory location pointed to by the address bus. a low rwla signal writes 18-bits of data to the location pointed by the address bus. the csa line has to be low to have port a respond to a read/write operation. in this configuration, rwha and rwhb are not used. the same operations on the b port are controlled by rwlb and csb . for this port, control signals and data interface with the grp. 256 x 18 dual port ram w/byte (9-bit) write in this mode, rwl is the control line which determines the type of operation to be performed on the lower 9 bits of the memory location. rwh is the control line used to select the type of operation to be performed on the higher 9 bits of the memory location. all other operating charac- teristics are similar to the previous mode. this mode is an ideal way to pack 9-bit data into 18-bit memory by simply alternating the rwl and rwh states. this mode can also be used to perform bus width conver- sion whereby one port operates at 9-bits and the second port operates at 18-bits 512 x 9 dual port ram this mode uses 9 address bits to select one of 512 locations. addra 0-7 form the 8 address bits and rwh is used as the 9th address bit (msb). in this configuration, the high order bits (bits 9-17) of the 18-bit data bus are used to transfer data to the ram. rwl is the control line used to select the type of operation to be performed on the specified memory location. arbitration the two ports may act like independent rams, however the arbitration and control logic as well as the memory core are shared by both ports as shown previously. when the cs is inactive the ram will ignore any opera- tion, read or write on that port. the dual port ram can be written to or read from asynchronously and simultaneously by each port at the same time (except for the same address). if the same address location is accessed by both ports, the arbitra- tion logic evaluates which port will win out. the port that wins will have a logic 1 or a busy inactive on its busy flag. busy will go low for the port that loses. if the address is the same for both ports and there is >5ns between the port accesses, the busy signal is activated and which port has to wait is determined on a first-come, first-served basis. when the addresses on port a and b are the same and the csa and csb both go low within 5ns of each other or if csa and csb are both low and the address for both ports change to the same location within 5ns, the arbitra- tion is unpredictable: either port may win. figure 20. dual port ram configurations a8/wrh busy a rwl cs global routing pool i/o cells rwha* busy a rwla cs a rwhb* busy b rwlb cs b oe dio 0-17 a0 - a7 addr a data in a data out a ram array 256 x 18 512 x 9 addr b data in b data out b 18 18 8 8 18 18
specifications isplsi 6192 17 figure 21. dual port ram with busy busy busy busy busy timing diagram addr b data in b rwhb and/or rwlb addr a b usya data out a t wc match valid match valid t wp t dw t dh t nba t aps t ba t nbd figure 22. dual port ram contention cycle ( cs cs cs cs cs arbitration) timing diagram figure 23. dual port ram contention cycle (address valid arbitration) timing diagram addr a b usy b addr b address match t rc or t wc t aps no address match t ba t nba addr a and b c s b c s a b usy b addresses match t aps t bcs t nbcs
specifications isplsi 6192 18 figure 24. dual port ram write cycle (rw controlled) timing diagram address c s o e rwl and/or rwh data out data in t wc t aw t wp t as t wedls t dw t dh t ween t wr t csdis t oedis figure 25. dual port ram write cycle ( cs cs cs cs cs controlled) timing diagram address c s rwl and/or rwh data in t wc t as t ewcs t dw t dh t aw t wr
specifications isplsi 6192 19 single port static ram constitutes the memory module in the 6192sm device. as a single-port memory, only one port is used to access the memory for data reads and writes. the 6192sm can be configured to operate either as one large single-port memory or as two smaller single- port memories. when used as a large single-port ram, the memory can be organized as 256 x 18 or 512 x 9. either port a or port b can be used to control the single-port ram as shown in figure 26. a byte read/write mode similar to that of the dual-port ram is also provided to allow independent control of the upper and lower 9-bit banks of the memory. when used as two independent smaller single-port memo- ries, each memory can be organized as 128 x 18 or 256 x 9. the two memories, however, must have identical configurations. port a, therefore controls one single-port memory and port b controls the other single-port memory as shown in figure 27. both memories can operate single port ram description (6192sm) simultaneously and independently. byte read/write mode also applies to the dual single-port ram configuration. when not used for memory interfacing, the dio0-8 (ram) and a3-a7 pins may be used for general purpose inputs into the grp. the ram is user configurable and can be configured as: single dual memory memory description port used ports used 128 x 18 single port ram a and b 128 x 18 single port ram a and b w/byte write (9 bit write) 256 x 9 single port ram a and b 256 x 18 single port ram a or b 256 x 18 single port ram a or b w/byte write (9 bit write) 512 x 9 single port ram a or b oe dio 0-17 18/9 ram array 128 x 18 256 x 9 and address decode control logic address b (addrb 0-7) rwhb rwlb csb data out b (0-17/0-8 to grp) data in b (0-17/0-8 from grp) ram array 128 x 18 256 x 9 address decode control logic address a (addra 0-7) rwha rwla csa 18/9 18/9 figure 26. single port ram functional block diagram (single ram block) ram array 256 x 18 512 x 9 or address decode control logic address b (addrb 0-7) rwhb rwlb csb data out b (0-17/0-8) data in b (0-17/0-8) ram array 256 x 18 512 x 9 address decode control logic address a (addra 0-7) rwha rwla csa oe dio 0-17 18/9 18/9 18/9 figure 27. single port ram functional block diagram (dual ram blocks)
specifications isplsi 6192 20 port a interfaces with the external world through the dedicated i/o pins and port b is internal to the device, through the grp. single port ram configurations 256 x 18 single port ram (port a or b) figure 28 shows the port a configuration of the single port ram. a0-7 form the 8-bit address bus used to select one of the 256 locations. rwla is the control line which determines the type of operation to be performed with the 18-bit data bus. a high rwla signal reads out 18-bits of data from the location pointed to by the address bus. a low rwla signal writes in 18-bits of data to the location pointed to by the address bus. the cs line has to be low (active-low) to have the ram respond to a read/write operation. as shown below, the control lines can come from the i/o cells and/or from the grp, as defined by the software. when in port b configuration (figure 29), the grp drives the address bus, data bus and the various control lines. 256 x 18 single port ram w/byte (9-bit) write (port a or b) in this mode, rwl is the control line which determines the type of operation to be performed on the lower 9 bits of the memory location using the lower 9-bits of the 18- bit data bus. similarly, rwh is the control line to select the type of operation to be performed using the higher 9 bits of the memory location with the higher 9 bits of the 18- bit data bus. all other operating characteristics are similar to the previous mode. 512 x 9 single port ram (port a or b) this mode uses 9 address bits to select one of the 512 locations. a0-a7 form the 8 address bits and rwh is used as the 9th address bit (msb). in this configuration, the higher 9 bits of the 18-bit data bus are used to transfer data. rwl is the control line used to select the type of operation to be performed on the specified memory location. the 6192sm can also be configured as two separate smaller single port rams with port a controlling one and port b controlling the other. both rams can operate simultaneously. each smaller memory operates exactly the same way as the larger memory except for the address bit a7. dual 128 x 18 single port ram (port a and b) this mode uses a0-a6 address bits to select one of the 128 locations. a7 is not used in this mode. rwla and csa control the operations for port a. rwlb and csb determine the operations for port b. dual 128 x 18 single port ram with byte write (port a and b) rwla and rwlb control the read/write operations for the lower order 9 bits of their respective memories. rwha and rwhb control the operation for the higher order 9 bits. dual 256 x 9 single port ram (port a and b) a7 is used as the most significant address bit required to access the 256 locations in the memory. the higher order 9 bits of the 18-bit bus are used to transfer data. rwl is the control line used to select the type of opera- tion to be performed. figure 28. single port ram: port a configuration ram array 256 x 18 512 x 9 global routing pool i/ocells a 0-7 addra data in a data out a a8/rwh note (*) 1. in 256 x 18 single port ram configuration, a8/rwh is left unconnected. 2. in 256 x 18 single port ram configuration with byte write configuration, a8/rwh acts as a control line to select the type of operation to be performed with the high 9 bits of the 18 bit data bus. 3. in 512 x 9 sin g le port ram confi g uration, a8/rwh is used as the most si g nificant address bit rwl cs a8/rwha* rwla cs a 8 oe 18/9 18/9 dio 0-17
specifications isplsi 6192 21 ram array 256 x 18 512 x 9 global routing pool addrb data in b data out b a8/rwhb rwlb cs b 18/9 8 18/9 figure 29. single port ram: port b configuration figure 30. single port ram read cycle timing diagram addr 0-7 o e c s rwl/rwh data out t rc t aoe t csen t ween t oeen t acs t aa t oh t oedis t csdis t wedis x y x y figure 31. single port ram write cycle ( cs cs cs cs cs controlled) timing diagram addr 0-7 c s rwl/rwh data in t wc t aw t as t ewcs, t wp t wr t dh t dw data in
specifications isplsi 6192 22 serial to serial the banks are addressed independently for read and write operations by using the three select (sel0-2) lines. these signals are driven from the 6192 grp. all eight banks can be configured as register files, but only four of them (banks 1,3,5,7) can be configured as 16 bit loadable up/down counters or as 16 bit loadable up/down modulo counters. each counter/timer bank can be individually configured by the user. the up/down mode and 8 or 16 bit operation of the counter/timer are configured when the device is programmed based upon the user s design the register/counter module consists of a group of eight 16-bit banks with control and data interfaces to both the grp and a dedicated group of device pins. the register file/counter has a 16-bit bidirectional parallel data inter- face, serial data in (sin), serial data out (sout), and output enable ( oe ) pins along with four carry out (cout) pins that correspond to the counter/timer func- tions described below. the banks in the register/ counter module can be configured by the user to imple- ment: registers counters timers (modulo counter) shift registers in addition, banks can be cascaded to form larger func- tions; for example, eight banks can be cascaded in the parallel-to-serial mode to form a 128-bit parallel-to-serial shift register. the ispds design software allows the designer to choose one of nine predefined configurations or modes for the register/counter module. depending on the mode cho- sen (discussed later), the data interfaces to the module can be configured as: parallel to parallel serial to parallel parallel to serial register/counter module description figure 32. register/counter module connectivity select inputs sel 2 0 0 0 0 1 1 1 1 sel 1 0 0 1 1 0 0 1 1 sel 0 0 1 0 1 0 1 0 1 bank # 0 1 2 3 4 5 6 7 bank selected mux 16 16 16 data in register/ counter 8 x 16 i/o cells data in (0-15) serial in grp enable sin data in data in (0-15) data out (0-15) serial out co/tc (0-3) data out (0-15) sout clk w/tc data out en serial in enable oe 16 4 4 4 count preload/start 4 carry in - count/hold 3 sel (0-2) shift enable serial out clock co/tc (0-3) clock
specifications isplsi 6192 23 inputs. all the eight word banks can be configured as shift registers. when the dedicated register/counter i/o pins (dio 0- 15) are not used for the register/counter module, they can be used as input-only pins for the general-purpose programmable logic block. in this mode, the data pins of the unused module feed directly into the device s global routing pool (grp). the data inputs, data outputs and the control signals for the register/counter module can be either active high or active low. other control signals (sen, sel0-2, etc.) come only from the grp. data inputs and sin and enable control signals can come from i/o cells or the grp. data output signals can go to i/o and the grp to be used in other logic. each bank can use a unique clock configuration. the clock is selectable from either one of the three glb clocks, the i/o clock 0 (y4) or a product term clock (ptck). the user has the ability to select the true or complement of the selected clock. there are two reset functions within the register/counter module, the global reset and pt bank reset. the global reset resets all the registers in programmable logic module and register/counter module. the global reset is active low. the product term (pt) bank reset, in conjunction with the select lines, is used to individually reset the banks. the pt bank reset is active high. the register/counter module i/o pins (dio 0-15 (rc))can be controlled by either the global output enable (goe) or the module output enable ( oe ) through a user- programmable option. the user has the choice of selecting either of these signals on an i/o by i/o basis. the oe can also be selected to be active high or low on an i/o by i/o basis. register/counter module configuration options there are nine pre-defined register/counter configura- tions or modes which are supported by lattice semiconductor s ispds software. these are: 1. 8-bank register file 2. 8-bank parallel to serial shift register 3. 8-bank serial to parallel shift register 4. 8-bank serial to serial shift register 5. 4-bank parallel load up/down counter with 4-bank register file 6. 4-bank adjacent load up/down counter with 4-bank adjacent register file 7. 4-bank parallel load up/down timer with 4-bank register file 8. 4-bank adjacent load up/down timer with 4-bank adjacent register file 9. 4-bank custom preset load up/down timer with 4-bank register file in the above modes, counters and timers can be loaded either 8 or 16 bits at a time. the following sections will discuss each of these operat- ing modes in detail. sel (0-2) 3 : 8 decoder product term bank reset b a n k 0123456 b a n k 7 3 figure 33. product term bank reset
specifications isplsi 6192 24 configuration #1: 8-bank register file the register file is organized as eight words of 16 bits each. sixteen data inputs are available to supply the data to be stored. the select lines permit direct access to read or write the data to any of these words. in order to write data to a location in the file, the sel0-2 lines must point to the correct location and the enable input must go active. the write operation is synchronous to the clock. data must be stable at the register/counter module inputs a minimum set-up time (tregsu) prior to low-to-high transition on the clock for it to be correctly written into the file. similarly, enable signal must be stable a minimum set-up time (tensu) prior to the low-to-high transition of the clock. data from the location pointed to by sel0-2 is always presented at the multiplexer outputs (data out 0- 15). however, to insure the data is valid, the read operation should be done when the enable is inactive or after the falling edge of the clock. for example, if the select line address is 011(binary) and the enable signal is low, the data is clocked into the bank 3. figure 34. register/counter option #1: 8-bank register file 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 en decoder d q bank 0 en d q en d q en d q en d q en d q en d q en d q clock 0 clock 2 clock 4 clock 6 data out 0-15 enable ( en ) data in 0-15 sel0 sel1 sel2 clock 1 clock 3 clock 5 clock 7 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7
specifications isplsi 6192 25 figure 35. register parallel read/write timing diagram data in data out sel 0-2 reset enable ( en ) clock t ssu t sh t regco t sco t ensu t enh t regsu t regh x x t grpw t clkh t clkl global oe t grdo reset to "0" t rgdis t rgen
specifications isplsi 6192 26 configuration #2: 8-bank parallel to serial shift register this configuration is used to convert data from a parallel to serial format. in this mode, each bank functions as a 16-bit shift register with all 8 bank s serially cascaded from bank 0 to bank 7 to form a 128-bit shift register chain. here, the parallel data write operation is the same as with the register file configuration. as previously discussed, the enable line must be low for the write operation to be performed. depending on the parallel load operation, the chain can be used as a 1-bit to 128- bit shift register. data is read out of the serial out (sout) pin (connected to the lsb of bank 7) serially on each clock transition when the shift enable ( sen ) is low. figure 36. register/counter option #2: 8-bank parallel to serial shift register 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 en d so si bank 0 en d en d en d en d en d en d en d shift enable ( sen ) enable ( en ) data in 0-15 sel0 sel1 sel2 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 so si so si so si so si so si so si decoder sout (from bit 0) clock
specifications isplsi 6192 27 figure 37. shift register parallel load/shift timing diagram figure 38. shift register serial load/shift timing diagram clock sin data out sel 0-2 shift enable ( sen ) t sensu t sinh t sinsu t regco clock data in sout sel 0-2 enable ( en ) shift enable ( sen ) t ssu t sh t ensu t enh t sensu t senh t regh t soutco t regsu
specifications isplsi 6192 28 configuration #3: 8-bank serial to parallel shift register this configuration is used to convert the data presented on the sin input from serial to parallel format. all 8 banks are cascaded together. the serial out line(lsb) of one bank is automatically connected to the next bank s serial in line (msb) and so on to form a 128-bit shift register. depending on the use of sel0-2, the shift register chain can be used as a 1-bit to 128-bit shift register. the serial write operation takes place when shift enable ( sen ) is low. the serial data is clocked into bank 0 (see figure 38). the read operation is same as parallel-to-parallel con- figuration. here also, the read operation should be performed when the enable is inactive or after the falling edge of the clock. 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 si q bank 0 qq q q qq q clock data out 0-15 shift enable ( sen ) sel0 sel1 sel2 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 serial in (to bit 15) so si so si so si so so so si si so si si figure 39. register/counter option #3: 8-bank serial to parallel shift register
specifications isplsi 6192 29 configuration #4: 8-bank serial to serial shift register this configuration is used to shift data in and serially shift data out. the bank are cascaded together to form a 128 bit shift register. the data flow is from the most signifi- cant bit (msb) to the least significant bit of each bank. the lsb of bank 0 is connected to the (msb) of bank 1 and so on. the serial data in (sin) is on bank 0 and the serial data out (sout) is on bank 7. both the read and write operations are serial in this mode of operation in this configuration. the shift enable signal controls the shift or hold activity of the data. when the shift enable is low, the banks will begin shifting data (msb to lsb) synchronously. when the signal is high, the banks retain the last data without shifting. figure 40. register/counter option #4: 8-bank serial to serial shift register 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 si bank 0 shift enable ( sen ) bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 serial in (to bit 15) so si so si so si so so so si si so si so sout (from bit 0) si clock
specifications isplsi 6192 30 configuration #5: 4 bank parallel load up/down counter with 4-bank register file four of the eight banks can be configured as 8- or 16-bit loadable, up or down counters. these word banks are bank 1, bank 3, bank 5 and bank 7. the counters are addressed for read and write operations in the same manner as the register file by using sel (0-2) and enable. the counters are parallel loaded from the data in (din) lines and are read out to the data out (dout) lines. the 8 or 16 bit data is loaded into the counter bank selected by the select lines. whether 8 or 16 bit data is transferred is determined by the operating mode defined for the specific counter when the device is programmed. load (write) occurs when enable (en) signal is low and a there is a low-to-high clock edge. each counter has independent carry in-count/hold (cich) and carry out (cout) lines, which allow the designer to have independent control of each counter, thus giving more flexibility in his design. these lines can have several alternative uses. the carry in and carry out lines can be used to cascade counters to form very large counters, up to 64 bits. the carry in can also be used as a count/hold control: when the signal is high, the counter will count. when low, it will hold the counter at the present count. the carry out line can also be used to tell when the counter has reached its maximum or terminal count (tc). the count operation will only take place when the carry in-count/hold is high and there is a low-to-high clock edge. when the counters reach ffffh during counting up or 0000h when counting down, their contents roll- over on the next clock pulse to 0000h and ffffh respectively, and counting continues, assuming carry-in is active (see figure 42). in mode #5, 4 banks (1,3,5,7) are configured as counters which operate as described immediately above, and 4 banks (0,2,4,6) operate as register files as described in mode #1 above. figure 41. register/counter option #5: 4 bank parallel load up/down counter with 4 bank register file 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 en d q bank 0 en co d c o u n t e r q ci en d q en d q en d q en co d c o u n t e r q ci en co d c o u n t e r q ci en co d c o u n t e r q ci carry in 0 carry in 1 carry in 2 carry in 3 (to bit 0) clock 0 clock 2 clock 4 clock 6 data out 0-15 enable ( en ) data in 0-15 sel0 sel1 sel2 carry out 0 carry out 1 carry out 2 carry out 3 (from bit 15) clock 1 clock 3 clock 5 clock 7 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 decoder
specifications isplsi 6192 31 figure 42. counter/timer timing diagram ci data in data out (counter) sel 0-2 enable ( en ) clock data out (timer) load data hold count co tc fd fe fe ff 00 ff fd fd t ssu t sh t ensu t cichsu t enh t cichl t regco t regsu t regh t caco
specifications isplsi 6192 32 configuration #6: 4 bank adjacent load up/down counter with 4 bank adjacent register file in this mode, the counters function as described in mode #5 above. however, rather than being parallel loaded from the data in lines when enable is low, the counters are loaded from the adjacent registers during a load. banks 0, 2, 4, 6 are used to hold the preload data for counter banks 1, 3, 5, and 7, respectively. the preload data is loaded into the selected register file bank in the usual manner when a clock occurs and the enable is low. data is loaded into the adjacent counter when th corre- sponding preload is low and there is a rising clock edge. figure 43. register/counter option #6: 4 bank adjacent load up/down counter with 4 bank adjacent register file 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 en d q bank 0 en co d c o u n t e r q ci en d q en d q en d q en co d c o u n t e r q ci en co d c o u n t e r q ci en co d c o u n t e r q ci carry in 0 carry in 1 carry in 2 carry in 3 (to bit 0) clock 0 clock 2 clock 4 clock 6 data out 0-15 preload 3 preload 2 preload 1 preload 0 enable ( en ) data in 0-15 sel0 sel1 sel2 carry out 0 carry out 1 carry out 2 carry out 3 (from bit 15) clock 1 clock 3 clock 5 clock 7 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 decoder
specifications isplsi 6192 33 configuration #7: 4 bank parallel load up/down timer with 4 bank register file four of the eight banks in the register/counter module can be configured as 8- or 16-bit loadable, up or down timers. these word banks are bank 1, bank 3, bank 5 and bank 7. the timers are addressed for loading and reading in the same manner as the register file (mode #1). the counters are parallel loaded from the data in (din) lines and are read out to the data out (dout) lines. the 8 or 16 bit data is loaded into the timer bank selected based on the operating mode specified for the timer and pro- grammed into the device. the load occurs when the enable signal is low and there is a rising clock edge. each timer has an independent carry in-count/hold line which allows the designer to have independent control of each timer, thus giving more flexibility. timer operation is different from counter operation in that a timer will stop counting once the terminal count (ffffh for an up timer and 0000h for a down timer) is reached. the timer will begin counting again only after the timer is reloaded using the enable and sel0-2 lines. also, each timer has a independent carry out/terminal count output. the carryin-count/hold and the count preload/start signals must be high for the timer to operate. in mode #7, 4 banks (1,3,5,7) are configured as timers which operate as described immediately above, and 4 banks (0,2,4,6) operate as registers as described in mode #1 above. 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 en d q bank 0 en co d t i m e r q ci en d q en d q en d q en co d t i m e r q ci en co d t i m e r q ci en co d t i m e r q ci count/hold 0 count/hold 1 count/hold 2 count/hold 3 (to bit 0) clock 0 clock 2 clock 4 clock 6 data out 0-15 enable ( en ) data in 0-15 sel0 sel1 sel2 terminal count 0 terminal count 1 terminal count 2 terminal count 3 (from bit 15) clock 1 clock 3 clock 5 clock 7 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 decoder figure 44. register/counter option #7: 4 bank parallel load up/down timer with 4 bank register file
specifications isplsi 6192 34 configuration #8: 4 bank adjacent load up/down timer with 4 bank adjacent register file in this mode, the timers function as described in mode #7 above. however, rather than being parallel loaded from the din lines when enable is low, the counters are loaded from the adjacent registers during a load. banks 0, 2, 4, 6 are used to hold the preload data for counter banks 1, 3, 5, and 7, respectively. the preload data is loaded into the selected register file bank in the usual manner when a clock occurs and the enable is low. data is loaded into the adjacent counter when preload is low and there is a rising clock edge. 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 en d q bank 0 en co d t i m e r q ci en d q en d q en d q en co d t i m e r q ci en co d t i m e r q ci en co d t i m e r q ci count/hold 0 count/hold 1 count/hold 2 count/hold 3 (to bit 0) clock 0 clock 2 clock 4 clock 6 data out 0-15 preload 3 preload 2 preload 1 preload 0 enable ( en ) data in 0-15 sel0 sel1 sel2 terminal count 0 terminal count 1 terminal count 2 terminal count 3 (from bit 15) clock 1 clock 3 clock 5 clock 7 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 decoder figure 45. register/counter option #8: 4 bank adjacent load up/down timer with 4 bank adjacent register file
specifications isplsi 6192 35 configuration #9: 4 bank custom preset load up/down timer with 4 bank register file these locations is loaded into the counter whenever preset is low and there is a clock edge. in mode #9, 4 banks (1,3,5,7) are configured as timers which operate as described immediately above, and 4 banks (0,2,4,6) operate as registers as described in mode #1 above. in this mode, the timers function as described in mode #7 above. however, rather than being parallel loaded from the din lines, or from the adjacent registers, in mode #9 the timers are loaded from dedicated e 2 prom (read- only memory) locations. the preset data in these locations is determined by the user when the logic is designed using the ispds software and is programmed into the device using non-volatile technology. the data from figure 46. register/counter option #9: 4 bank custom preset load up/down timer with 4 bank register file 15 0 15 0 15 0 15 0 15 0 15 0 15 0 15 0 en d q bank 0 en co d t i m e r q ci en d q en d q en d q en co d t i m e r q ci en co d t i m e r q ci en co d t i m e r q ci count/hold 0 count/hold 1 count/hold 2 count/hold 3 (to bit 0) clock 0 note: = e 2 prom cell clock 2 clock 4 clock 6 data out 0-15 preset 3 preset 2 preset 1 preset 0 enable ( en ) data in 0-15 sel0 sel1 sel2 terminal count 0 terminal count 1 terminal count 2 terminal count 3 (from bit 15) clock 1 clock 3 clock 5 clock 7 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 decoder
specifications isplsi 6192 36 selects which signal will be used, and its polarity. there is also a software programmable slew rate control. slew rate control allows non-timing-critical signals to run at a slower rate which improves system noise immunity. the software has the capability to enable and disable the slew rate control bit on an individual i/o basis. when the i/o cell is used as an input, the data goes to the input register and a selection multiplexer which selects either the direct data input or the input register output. the output of the multiplexer then goes to the grp. the input register can be configured as a level sensitive transparent latch or an edge triggered d-type flip-flop to store the incoming data. each i/o cell can individually select one of the two clock signals (ioclk 0 or ioclk 1). the input register reset signal is hard wired to the global reset ( reset ) signal which is driven by the active low chip reset pin. there is an active pull-up resistor on the i/o pins which is automatically used when the pin is not used in the design. this improves the noise immunity and reduces i cc for the device. an option exists to have active pull-up resistors connected to all pins. the 6192 family of devices has 3 types of programmable i/o cells. they can be classified as: ? general bidirectional i/o cell ? module bidirectional i/o cell ? module i/o cell general bidirectional i/o cell the general bidirectional i/o cell structure, associated with megablocks a, b, c, d, e and f is similar to lattice semiconductor s 3000 family i/o cells (see figure 47). they are used to route input, output or bi-directional signals connected to the i/o pin. each i/o cell contains boundary scan registers (see boundary scan section). a global test oe signal is hardwired to all i/o cells and is used to 3-state all output buffers within the device. in addition to the test oe signal, two software selectable global oes are connected to each of these i/o cells. a product term oe and global oe signals are fed to an oe multiplexer to allow one of the three signals to control the output. this oe signal can also be inverted. the output signal can come from one of two sources, the orp or the faster orp bypass. a pair of multiplexers i/o cells from orp bypass from orp output enable ioclk 0 ioclk 1 to global routing pool from global reset global oe0 mux dq r/l reset mux mux mux i/o pin programmable pullup global oe1 product term oe mux mux test oe note: 1. represents an e 2 cmos cell. 2. see boundary scan section for details. 0138a/3256 note 2 slew figure 47. general-purpose bidirectional i/o cell
specifications isplsi 6192 37 module bidirectional i/o cell module bidirectional i/o cells are associated with the bidirectional data bus in the memory module and the register/counter module. the structure of these cells is similar to that of the general bi-directional i/o cells, with some differences. figure 48 illustrates two signals that are hard-wired to module data i/o cells: test oe and cs/ rw. test oe is driven by the toe pin and is wired to all the module data i/o cells. cs/rw is generated by logic internal to the memory module and is only wired to the data i/o cells associated with this module. cs/rw is high only when the chip is selected and the memory is to be read. thus, an inactive chip select forces the pin driver in each of these i/o cells to the high impedance state. figure 48 shows pin oe , product term oe, and two global oe signals. these are fed to an oe multiplexer to allow one of these four signals or its inversion to control the output driver. the logic output from the register/ counter module has an inversion capability in the i/o cell while the memory module does not (see figure 48, note 4). selected data i/o cells (0-8) in the memory module have an alternative use: these pins can be used as general- purpose inputs to the grp when the memory module is used in 512 x 9 configuration or left unused in the design. the data i/o cells (0-15) in the register/counter module can also be used as general-purpose inputs to the grp provided the register/counter module is left unused in the design (see figure 48, note 3). in the module bidirectional i/o cell, unlike in the general bidirectional i/o cell where the slew rate is individually controllable for each outputs, either all or none of the output data bits can be programmed to have slew rate control. figure 48. module bidirectional i/o cell from module output enable to global routing pool to module global oe0 mux mux i/o pin programmable pullup global oe1 product term oe pin oe mux mux cs/rw test oe note: 1. represents an e 2 cmos cell. 2. see boundary scan section for details. 3. selected module i/o pins only (dio0-8(mem) and dio0-15(rc)) 4. register/counter module data i/o cell only. 5. memory module data i/o cell only. 0139a/6192 note 2 note 3 slew note 4 note 5
specifications isplsi 6192 38 module i/o cell module i/o cells are associated with the logic control signals of the memory module and register/counter mod- ule. they are controlled by the software and can be programmed as simple inputs or outputs. a multiplexer is used to select the polarity of the output signal coming from the module. the control signals (tc/co(0-3), sout) of the register/ counter module use output pins. the slew rate is individu- ally controllable for each output. sin and enable are input pins. selected i/o cells in the memory module can be used as general-purpose logic inputs if the memory module is left unused (see figure 49, note 3). the table below summarizes various types of i/o cells used by the module. they are classified as module bidirectional i/o cells and module unidirectional i/o cells. the output signals come from the module. some of them can be configured with the help of a polarity selection multiplexer. when the i/o cell is used as an input, the data goes to the module. some of the i/o cells have an additional capability of being used as inputs to the grp when the module is left unused in the design. module unidirectional i/o cells can be used either as an input or an output. when used as an output cell, toe will always 3-state the output buffer. it also has a program- mable slew rate control. when used as an input cell as shown in the table there are two versions: one that drives the module only, and a second version which can drive the grp if the module is not used. figure 49. module i/o cell from module output enable to global routing pool to module mux mux i/o pin programmable pullup mux test oe +5 note: 1. represents an e 2 cmos cell. 2. see boundary scan section for details. 3. only in memory module ( ale & alf in fifo and a3 - a7 in ram). 0140a/6192 note 2 note 3 slew
specifications isplsi 6192 39 module i/o cell connectivity e m a n l a n g i s l l e c o / i l a n o i t c e r i d i b e l u d o m l l e c o / i l a n o i t c e r i d i n u e l u d o m c i s a b o t t u p n i t u p t u o m o r f e l u d o m c i s a b o t t u p n i t u p t u o m o r f e l u d o m e l u d o mp r ge l u d o mp r g / r e t s i g e r r e t n u o c e c a f r e t n i 5 1 - 0 o i d 2 ?? 3 t u o s , 3 - 0 o c / c t 1 3 e o , n i s , e l b a n e o f i f e c a f r e t n i 8 - 0 o i d 2 ?? 7 1 - 9 o i d 2 ? f e , f f 1 ? 3 e l a , f l a 1 ?? 3 t s r , e o , d r r o r w m a r e c a f r e t n i 8 - 0 o i d 2 ?? 7 1 - 9 o i d 2 ? , 0 a e o l w r , 2 a , 1 a 1 4 a , 3 a 1 ? 7 a , 6 a , 5 a ? , h w r / 8 a s c ? : e t o n . s l o r t n o c e t a r w e l s e l b a m m a r g o r p d n a e o t . 1 . s l o r t n o c e t a r w e l s e l b a m m a r g o r p d n a e o t , e o t p , e o g . 2 . r e x e l p i t l u m n o i t c e l e s y t i r a l o p t u p t u o . 3
specifications isplsi 6192 40 absolute maximum ratings 1 supply voltage v cc .................................. -0.5 to +7.0v input voltage applied ........................ -2.5 to v cc +1.0v off-state output voltage applied ..... -2.5 to v cc +1.0v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating condition t a symbol table 2 - 0005/3256 v cc v ih v il parameter ambient temperature supply voltage input high voltage input low voltage min. max. units 0 4.75 2.0 0 70 5.25 v +1 0.8 c v v v cc capacitance (t a =25 c,f=1.0 mhz) symbol table 2 - 0006/6192 c parameter clock capacitance 15 units typical test conditions 2 pf v = 5.0v, v = 2.0v cc y c i/o capacitance 10 1 pf v = 5.0v, v = 2.0v cc i/o data retention specifications table 2- 0008b parameter data retention minimum maximum units isplsi erase/reprogram cycles 20 10000 years cycles
specifications isplsi 6192 41 switching test conditions input pulse levels table 2 - 0003 input rise and fall time input timing reference levels output timing reference levels output load gnd to 3.0v 3ns 10% to 90% 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. output load conditions (see figure 50) test condition r1 r2 cl a 470 ? 390 ? 35pf b 390 ? 35pf 470 ? 390 ? 35pf active high active low c 470 ? 390 ? 5pf 390 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2 - 0004a + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a dc electrical characteristics over recommended operating conditions figure 50. test load l o b m y sr e t e m a r a pn o i t i d n o c. n i m. p y t 3 . x a ms t i n u v l o e g a t l o v w o l t u p t u oi l o a m 8 = 4 . 0v v h o e g a t l o v h g i h t u p t u oi h o a m 4 - =4 . 2 v i l i t n e r r u c e g a k a e l w o l o / i r o t u p n iv 0 v l o v l i ) . x a m ( 0 1 - a i h i t n e r r u c e g a k a e l h g i h o / i r o t u p n iv 5 . 3 v n i v c c 0 1 a i u p - l i t n e r r u c p u - l l u p e v i t c a o / iv 0 v n i v l i ) . x a m ( 0 5 1 - a i p s i - l i / n a c s b n e p s i e g a k a e l w o l t u p n i t n e r r u c v 0 v n i v l i ) . x a m ( 0 5 1 - a i s o t n e r r u c t i u c r i c t r o h s t u p t u ov c c v , v 5 = t u o v 5 . 0 = 0 0 2 -a m i c c 4 , 2 t n e r r u c y l p p u s r e w o p g n i t a r e p ov l i v , v 0 = h i f , v 0 . 3 = e l g g o t z h m 1 = 0 5 1 a m v . d n o c e s e n o f o n o i t a r u d m u m i x a m a r o f e m i t a t a t u p t u o e n o . 1 t u o r e t s e t y b s m e l b o r p t s e t d i o v a o t d e t c e l e s s a w v 5 . 0 = . d e t s e t % 0 0 1 t o n t u b d e e t n a r a u g . n o i t a d a r g e d d n u o r g . s r e t n u o c t i b - 6 1 n e e t x i s g n i s u d e r u s a e m . 2 v t a e r a s e u l a v l a c i p y t . 3 c c t d n a v 5 = a 5 2 = . c i m u m i x a m . 4 c c n o i t p m u s n o c r e w o p e h t o t r e f e r . y c n e u q e r f g n i t a r e p o d n a n o i t a r u g i f n o c e c i v e d c i f i c e p s h t i w y l e d i w s e i r a v o t m o r - d c r o k o o b a t a d r o t c u d n o c i m e s e c i t t a l e h t f o n o i t c e s t n e m e g a n a m l a m r e h t d n a t e e h s a t a d s i h t f o n o i t c e s i m u m i x a m e t a m i t s e c c .
specifications isplsi 6192 42 external switching characteristics: programmable logic module 1, 2, 3 over recommended operating conditions r e t e m a r a p t s e t 5 . d n o c # 2 n o i t p i r c s e d 1 0 7 -0 5 - s t i n u . n i m. x a m. n i m. x a m t 1 d p a1 s s a p y b p r o , s s a p y b t p 4 , y a l e d n o i t a g a p o r p a t a d 5 1 0 2s n t 2 d p a2 y a l e d n o i t a g a p o r p a t a d 8 1 5 . 4 2s n f ) . t n i ( x a m a3 k c a b d e e f l a n r e t n i h t i w y c n e u q e r f k c o l c 3 7 7 7 5 z h m f ) . t x e ( x a m 4k c a b d e e f l a n r e t x e h t i w y c n e u q e r f k c o l c0 5 7 3 z h m f ) . g o t ( x a m 5e l g g o t x a m , y c n e u q e r f k c o l c 4 3 8 3 6 z h m t 1 u s 6s s a p y b t p 4 , k c o l c e r o f e b e m i t p u t e s . g e r b l g5 . 9 5 . 2 1 s n t 1 o c a7 s s a p y b p r o , y a l e d t u p t u o o t k c o l c . g e r b l g 9 2 1s n t 1 h 8s s a p y b t p 4 , k c o l c r e t f a e m i t d l o h . g e r b l g0 0 s n t 2 u s 9k c o l c e r o f e b e m i t p u t e s . g e r b l g1 1 5 1 s n t 2 o c 0 1y a l e d t u p t u o o t k c o l c . g e r b l g 5 . 0 1 4 1s n t 2 h 1 1k c o l c r e t f a e m i t d l o h . g e r b l g0 0 s n t 1 r a2 1y a l e d t u p t u o o t n i p t e s e r . t x e 5 1 0 2s n t 1 w r 3 1n o i t a r u d e s l u p t e s e r . t x e0 1 5 . 3 1 s n t n e e o t p b4 1e l b a n e t u p t u o o t t u p n i 8 1 5 . 4 2s n t s i d e o t p c5 1e l b a s i d t u p t u o o t t u p n i 8 1 5 . 4 2s n t n e e o g b6 1e l b a n e t u p t u o e o l a b o l g 1 1 5 . 3 1s n t s i d e o g c7 1e l b a s i d t u p t u o e o l a b o l g 1 1 5 . 3 1s n t n e e o t b8 1e l b a n e t u p t u o e o t s e t 7 1 3 2s n t s i d e o t c9 1e l b a s i d t u p t u o e o t s e t 7 1 3 2s n t h w 0 2h g i h , n o i t a r u d e s l u p k c o l c . c n y s . t x e4 5 s n t l w 1 2w o l , n o i t a r u d e s l u p k c o l c . c n y s . t x e4 5 s n t 3 u s 2 2) 4 y , 3 y ( k c o l c . c n y s . t x e e r o f e b e m i t p u t e s . g e r o / i6 8 s n t 3 h 3 2) 4 y , 3 y ( k c o l c . c n y s . t x e r e t f a e m i t d l o h . g e r o / i0 0 s n . p r o d n a h t a p r o x t p 0 2 e s u s r e t e m a r a p l l a , e s i w r e h t o d e t o n s s e l n u . 1 . s l i a t e d r e h t r u f r o f t e e h s a t a d s i h t n i l e d o m g n i m i t o t r e f e r . 2 . k c a b d e e f p r g g n i s u r e t n u o c t i b - 6 1 d r a d n a t s . 3 . % 0 5 n a h t r e h t o f o e l c y c y t u d k c o l c a r o f w o l l a o t s i s i h t . ) l w t + h w t ( / 1 n a h t s s e l e b y a m ) e l g g o t ( x a m f . 4 . n o i t c e s s n o i t i d n o c t s e t g n i h c t i w s e c n e r e f e r . 5
specifications isplsi 6192 43 internal timing parameters: programmable logic module 1 over recommended operating conditions t iobp 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2 - 0036a/6192 inputs units -70 min. -50 min. max. max. description # 2 parameter 24 i/o register bypass 3.3 ns t iolat 25 i/o latch delay 15.8 ns t iosu 26 i/o register setup time before clock 9.6 ns t ioh 27 i/o register hold time after clock -7.0 ns grp t ioco 28 i/o register clock to out delay 5.3 ns t ior 29 i/o register reset to out delay 4.9 ns t grp 30 grp delay 4.1 ns glb t 4ptbp 31 4 product term bypass path delay 7.6 ns t 1ptxor 32 1 product term/xor path delay 8.8 ns t 20ptxor 33 20 product term/xor path delay 10.1 ns t xoradj 34 xor adjacent path delay 11.1 ns t gbp 35 glb register bypass delay 0.1 ns t gsu 36 glb register setup time before clock 2.4 ns t gh 37 glb register hold time after clock 8.2 ns t gco 38 glb register clock to output delay 2.2 ns 3 t gro 39 glb register reset to output delay 3.8 ns t ptre 40 glb product term reset to register delay 14.2 ns t ptoe 41 glb product term output enable to i/o cell delay 7.3 ns t ptck 42 glb product term clock delay 4.3 8.5 ns orp t orp 43 orp delay 3.6 ns t orpbp 44 orp bypass delay 1.6 ns 7.2 -5.2 1.8 6.0 2.4 12.4 4.2 3.6 3.0 5.9 6.4 7.4 8.1 0.1 1.8 2.8 10.5 5.4 3.2 6.3 2.7 1.2
specifications isplsi 6192 44 internal timing parameters: programmable logic module 1 over recommended operating conditions t ob 1. internal timing parameters are not tested and are for reference only. 2. refer to timin g model in this data sheet for further details. table 2 - 0037a/3256 outputs units -70 min. -50 min. max. max. description # 2 parameter 45 output buffer delay 3.3 ns t oen 47 i/o cell oe to output enabled 9.8 ns t odis 48 i/o cell oe to output disabled 9.8 ns t gy0/1/2 49 clock delay, y0 or y1 or y2 to global glb clock line 4.9 4.9 ns t ioy3/4 50 clock delay, y3 or y4 to i/o cell global clock line 1.6 7.0 ns global reset t gr 51 global reset to glb and i/o registers 9.6 ns clocks 2.4 7.2 7.2 t obs 46 output buffer delay, slow slew 13.3 ns 12.4 3.6 3.6 1.2 5.2 7.1
specifications isplsi 6192 45 external switching characteristics: fifo module 1 over recommended operating conditions r e t e m a r a p t s e t 2 . d n o c # 1 n o i t p i r c s e d 0 7 -0 5 - s t i n u . n i m. x a m. n i m. x a m t s 2 5y c n e u q e r f t f i h s 0 5 3 . 3 3z h m t c r a3 5e m i t e l c y c d a e r0 2 0 3 s n t a a4 5e m i t s s e c c a a t a d o t e s l u p d a e r 2 1 0 2s n t r r a5 5e m i t y r e v o c e r d a e r5 0 1 s n t w p r 6 5h t d i w e s l u p d a e r5 1 0 2 s n t v d a7 5e v i t c a n i e s l u p d a e r m o r f d i l a v d l e h a t a d3 3 s n t c w 8 5e m i t e l c y c e t i r w0 2 0 3 s n t w p w 9 5h t d i w e s l u p e t i r w5 1 0 2 s n t r w 0 6e m i t y r e v o c e r e t i r w5 0 1 s n t s d 1 6e m i t p u t e s a t a d3 1 8 1 s n t h d 2 6e m i t d l o h a t a d0 0 s n t c s r 3 6e m i t e l c y c t e s e r0 2 0 3 s n t s r 4 6h t d i w e s l u p t e s e r5 1 0 2 s n t r s r a5 6e m i t y r e v o c e r t e s e r5 0 1 s n t l f e a6 6e v i t c a g a l f y t p m e o t e v i t c a t e s e r 0 2 5 2s n t h f f a7 6e v i t c a n i g a l f l l u f o t e v i t c a t e s e r 0 2 5 2s n t l e l a a8 6e v i t c a g a l f y t p m e t s o m l a o t e v i t c a t e s e r 5 2 0 3s n t h f l a a9 6e v i t c a n i g a l f l l u f t s o m l a o t e v i t c a t e s e r 5 2 0 3s n t f f r a0 7e v i t c a n i g a l f l l u f o t e v i t c a n i d a e r 0 2 5 2s n t f a r a1 7e v i t c a n i g a l f l l u f t s o m l a o t e v i t c a n i d a e r 5 2 0 3s n t z h r a2 7e l b a s i d t u o a t a d o t e v i t c a n i d a e r 5 1 0 2s n t z l r a3 7e l b a n e t u o a t a d o t e v i t c a d a e r0 0 s n t s s r a4 7e v i t c a n i t e s e r o t e v i t c a n i e t i r w r o d a e r5 1 0 2 s n t e a r a5 7e v i t c a g a l f y t p m e t s o m l a o t e v i t c a d a e r 5 2 0 3s n t f e r a6 7e v i t c a y t p m e o t e v i t c a d a e r 0 2 5 2s n t e p r a7 7e v i t c a n i g a l f y t p m e r e t f a h t d i w e s l u p d a e r5 1 0 2 s n t f f w 8 7e v i t c a g a l f l l u f o t e v i t c a e t i r w 0 2 5 2s n t f a w 9 7e v i t c a g a l f l l u f t s o m l a o t e v i t c a e t i r w 5 2 0 3s n t e a w 0 8e v i t c a n i g a l f y t p m e t s o m l a o t e v i t c a n i e t i r w 5 2 0 3s n t f e w 1 8e v i t c a n i g a l f y t p m e o t e v i t c a n i e t i r w 0 2 5 2s n t f p w 2 8e v i t c a n i g a l f l l u f r e t f a h t d i w e s l u p e t i r w5 1 0 2 s n . s l i a t e d r e h t r u f r o f t e e h s a t a d s i h t n i l e d o m g n i m i t o t r e f e r . 1 . n o i t c e s s n o i t i d n o c t s e t g n i h c t i w s e c n e r e f e r . 2
specifications isplsi 6192 46 internal timing parameters: fifo module 1 over recommended operating conditions r e t e m a r a p #n o i t p i r c s e d 0 7 -0 5 - s t i n u . n i m. x a m. n i m. x a m t s 3 8y c n e u q e r f t f i h s 0 5 5 . 8 2z h m t c r 4 8e m i t e l c y c d a e r 5 2 5 3 s n t v d r e 5 8d i l a v a t a d t x e n o t e s l u p d a e r d n e 2 1 0 2s n t r r 6 8e m i t y r e v o c e r d a e r 0 1 5 1 s n t w p r 7 8h t d i w e s l u p d a e r 5 1 0 2 s n t c w 8 8e m i t e l c y c e t i r w0 2 0 3 s n t w p w 9 8h t d i w e s l u p e t i r w5 1 0 2 s n t r w 0 9e m i t y r e v o c e r e t i r w5 0 1 s n t s d 1 9e m i t p u t e s a t a d 8 1 3 2 s n t h d 2 9e m i t d l o h a t a d0 0 s n t c s r 3 9e m i t e l c y c t e s e r 5 2 0 3 s n t s r 4 9h t d i w e s l u p t e s e r 5 1 0 2 s n t r s r 5 9e m i t y r e v o c e r t e s e r 0 1 0 1 s n t l f e 6 9e v i t c a g a l f y t p m e o t e v i t c a t e s e r 5 1 8 1s n t h f f 7 9e v i t c a n i g a l f l l u f o t e v i t c a t e s e r 5 1 8 1s n t l e l a 8 9e v i t c a g a l f y t p m e t s o m l a o t e v i t c a t e s e r 0 2 3 2s n t l f l a 9 9e v i t c a n i g a l f l l u f t s o m l a o t e v i t c a t e s e r 0 2 3 2s n t f f r 0 0 1e v i t c a n i g a l f l l u f o t e v i t c a n i d a e r 5 1 8 1s n t f a r 1 0 1e v i t c a n i g a l f l l u f t s o m l a o t e v i t c a n i d a e r 0 2 3 2s n t s s r 2 0 1e v i t c a n i t e s e r o t e v i t c a n i e t i r w r o d a e r 5 1 0 2 s n t e a r 3 0 1e v i t c a g a l f y t p m e t s o m l a o t e v i t c a d a e r 0 2 3 2s n t f e r 4 0 1e v i t c a y t p m e o t e v i t c a d a e r 5 1 8 1s n t e p r 5 0 1e v i t c a n i g a l f y t p m e r e t f a h t d i w e s l u p d a e r 5 1 0 2 s n t f f w 6 0 1e v i t c a g a l f l l u f o t e v i t c a e t i r w 5 1 8 1s n t f a w 7 0 1e v i t c a g a l f l l u f t s o m l a o t e v i t c a e t i r w 0 2 3 2s n t e a w 8 0 1e v i t c a n i g a l f y t p m e t s o m l a o t e v i t c a n i e t i r w 0 2 3 2s n t f e w 9 0 1e v i t c a n i g a l f y t p m e o t e v i t c a n i e t i r w 5 1 8 1s n t f p w 0 1 1e v i t c a n i g a l f l l u f r e t f a h t d i w e s l u p e t i r w5 1 0 2 s n h t a p c i r e n e g t o i m m e m 1 1 1o i m o t t u o y r o m e m r o f d e d d a y a l e d 1 2s n f p r g m e m 2 1 1p r g o t t u o y r o m e m r o f d e d d a y a l e d 1 2s n t m e m o i m 3 1 1y r o m e m o t o i m r o f d e d d a y a l e d 4 5s n t m e m p r g 4 1 1y r o m e m o t p r g r o f d e d d a y a l e d 4 5s n . y l n o e c n e r e f e r r o f e r a d n a d e t s e t t o n e r a s r e t e m a r a p g n i m i t l a n r e t n i . 1
specifications isplsi 6192 47 external switching characteristics: ram module (port a only) 1 over recommended operating conditions r e t e m a r a p t s e t 2 . d n o c # 1 n o i t p i r c s e d 0 7 -0 5 - s t i n u . n i m. x a m. n i m. x a m e l c y c d a e r t c r 5 1 1e m i t e l c y c d a e r0 2 5 2 s n t a a a6 1 1e m i t s s e c c a s s e r d d a 0 2 5 2s n t s c a a7 1 1e m i t s s e c c a t c e l e s p i h c 5 1 0 2s n t e o a a8 1 1e m i t s s e c c a n i p e o 2 1 5 1s n t h o a9 1 1e g n a h c s s e r d d a m o r f d l o h t u p t u o2 2 s n t n e e o b0 2 1e l b a n e t u p t u o a t a d o t n i p e o0 0 s n t s i d e o c1 2 1e l b a s i d t u p t u o a t a d o t n i p e o 2 1 5 1s n t n e s c b2 2 1e l b a n e t u p t u o a t a d o t t c e l e s p i h c0 0 s n t s i d s c c3 2 1e l b a s i d t u p t u o a t a d o t t c e l e s p i h c 5 1 0 2s n e l c y c e t i r w t c w 4 2 1e m i t e l c y c e t i r w0 2 5 2 s n t w a 5 2 1d n e e t i r w o t d i l a v s s e r d d a5 1 0 2 s n t s a 6 2 1t r a t s e t i r w o t p u t e s s s e r d d a0 0 s n t ) w c t ( s c w e 7 2 1e t i r w f o d n e o t t c e l e s p i h c5 1 0 2 s n t p w 8 2 1h t d i w e s l u p e t i r w5 1 0 2 s n t r w 9 2 1e m i t y r e v o c e r e t i r w0 0 s n t w d 0 3 1d n e e t i r w o t d i l a v a t a d5 1 0 2 s n t h d 1 3 1d n e e t i r w m o r f d l o h a t a d0 0 s n t n e e w 2 3 1e l b a n e t u p t u o a t a d o t h g i h w r0 0 t s i d e w 3 3 1e l b a s i d t u p t u o a t a d o t w o l w r 5 1 0 2s n g n i m i t y s u b t a b 4 3 1h c t a m s s e r d d a m o r f y s u b 5 1 0 2s n t a b n 5 3 1h c t a m s i m s s e r d d a m o r f y s u b t o n 5 1 0 2s n t s c b 6 3 1e v i t c a t c e l e s p i h c m o r f y s u b 5 1 0 2s n t s c b n 7 3 1e v i t c a n i t c e l e s p i h c m o r f y s u b t o n 5 1 0 2s n t s p a 8 3 1e m i t p u t e s y t i r o i r p n o i t a r t i b r a5 8 s n t d b n 9 3 1d i l a v a t a d d a e r o t y s u b t o n 0 2 0 3s n . s l i a t e d r e h t r u f r o f t e e h s a t a d s i h t n i l e d o m g n i m i t o t r e f e r . 1 . n o i t c e s s n o i t i d n o c t s e t g n i h c t i w s e c n e r e f e r . 2
specifications isplsi 6192 48 internal timing parameters: ram module (port b only) over recommended operating conditions r e t e m a r a p #n o i t p i r c s e d 0 7 -0 5 - s t i n u . n i m. x a m. n i m. x a m e l c y c d a e r t c r 0 4 1e m i t e l c y c d a e r5 2 0 3 s n t a a 1 4 1e m i t s s e c c a s s e r d d a 0 2 8 2s n t h o 2 4 1e g n a h c s s e r d d a m o r f d l o h t u p t u o0 0 s n e l c y c e t i r w t c w 3 4 1e m i t e l c y c e t i r w5 2 0 3 s n t w a 4 4 1d n e e t i r w o t d i l a v s s e r d d a7 1 2 2 s n t s a 5 4 1t r a t s e t i r w o t p u t e s s s e r d d a0 0 s n t ) w c t ( s c w e 6 4 1e t i r w f o d n e o t t c e l e s p i h c7 1 2 2 s n t p w 7 4 1h t d i w e s l u p e t i r w5 1 0 2 s n t r w 8 4 1e m i t y r e v o c e r e t i r w0 0 s n t w d 9 4 1d n e e t i r w o t d i l a v a t a d7 1 2 2 s n t h d 0 5 1d n e e t i r w m o r f d l o h a t a d0 0 s n g n i m i t y s u b t a b 1 5 1h c t a m s s e r d d a m o r f y s u b 0 1 3 1s n t a b n 2 5 1h c t a m s i m s s e r d d a m o r f y s u b t o n 0 1 3 1s n t s c b 3 5 1e v i t c a t c e l e s p i h c m o r f y s u b 0 1 3 1s n t s c b n 4 5 1e v i t c a n i t c e l e s p i h c m o r f y s u b t o n 0 1 3 1s n t s p a 5 5 1e m i t p u t e s y t i r o i r p n o i t a r t i b r a5 8 s n t d b n 6 5 1d i l a v a t a d d a e r o t y s u b t o n 0 2 0 3s n h t a p c i r e n e g t o i m m e m 7 5 1o i m o t t u o y r o m e m r o f d e d d a y a l e d 1 2s n f p r g m e m 8 5 1p r g o t t u o y r o m e m r o f d e d d a y a l e d 1 2s n t m e m o i m 9 5 1y r o m e m o t o i m r o f d e d d a y a l e d 4 5s n t m e m p r g 0 6 1y r o m e m o t p r g r o f d e d d a y a l e d 4 5s n
specifications isplsi 6192 49 external switching characteristics: register/counter module 1 over recommended operating conditions r e t e m a r a p t s e t 2 . d n o c # 1 n o i t p i r c s e d 0 7 -0 5 - s t i n u . n i m. x a m. n i m. x a m t o c g e r a1 6 1t u o a t a d l e l l a r a p o t k c o l c 5 1 0 2s n t u s g e r 2 6 1k c o l c o t p u t e s n i a t a d l e l l a r a p8 2 1 s n t h g e r 3 6 1k c o l c m o r f d l o h n i a t a d l e l l a r a p0 0 s n t o d r g a4 6 1t u o a t a d o t t e s e r l a b o l g 0 2 5 2s n t w p r g 5 6 1n o i t a r u d e s l u p t e s e r l a b o l g2 1 5 1 s n t n e g r b6 6 1e l b a n e t u p t u o e o l a b o l g 5 1 0 2s n t s i d g r c7 6 1e l b a s i d t u p t u o e o l a b o l g 5 1 0 2s n t h k l c 8 6 1d o i r e p h g i h k c o l c4 5 s n t l k l c 9 6 1d o i r e p w o l k c o l c4 5 s n r e t s i g e r t f i h s t t f s 0 7 1e t a r t f i h s . x a m , y c n e u q e r f k c o l c5 2 1 0 0 1 z h m t o c t u o s 1 7 1t u o s o t k c o l c 7 1 0 2s n t u s n i s 2 7 1k c o l c o t p u t e s n i s8 2 1 s n t h n i s 3 7 1k c o l c m o r f d l o h n i s0 0 s n r e m i t / r e t n u o c f x a m 4 7 1r e t n u o c t i b - 6 15 2 1 0 0 1 z h m f x a m 5 7 1r e m i t t i b - 6 15 2 1 0 0 1 z h m t o c a c a6 7 1) t i b - 6 1 ( c t / t u o y r r a c o t k c o l c 8 1 2 2s n . s l i a t e d r e h t r u f r o f t e e h s a t a d s i h t n i l e d o m g n i m i t o t r e f e r . 1 . n o i t c e s s n o i t i d n o c t s e t g n i h c t i w s e c n e r e f e r . 2
specifications isplsi 6192 50 internal timing parameters: register/counter module over recommended operating conditions r e t e m a r a p #n o i t p i r c s e d 0 7 -0 5 - s t i n u . n i m. x a m. n i m. x a m s g n i m i t c i r e n e g t o c s 7 7 1t u o a t a d l e l l a r a p o t t c e l e s 6 . 4 1 6 . 7 1s n t u s s 8 7 1k c o l c o t p u t e s t c e l e s6 . 7 9 . 1 1 s n t h s 9 7 1k c o l c o t d l o h t c e l e s0 0 s n t u s n e 0 8 1k c o l c o t p u t e s t e s e r p / d a o l e r p / e l b a n e6 . 7 9 . 1 1 s n t h n e 1 8 1k c o l c m o r f d l o h t e s e r p / d a o l e r p / e l b a n e0 0 s n t o d r t p 2 8 1t u o a t a d o t t e s e r m r e t t c u d o r p 9 . 1 1 4 . 3 1s n t w p r t p 3 8 1n o i t a r u d e s l u p t e s e r m r e t t c u d o r p2 1 5 1 s n r e t s i g e r t f i h s t u s n e s 4 8 1k c o l c o t p u t e s n e t f i h s6 . 7 9 . 1 1 s n t h n e s 5 8 1k c o l c o t d l o h n e t f i h s0 0 s n r e m i t / r e t n u o c t o c a c 6 8 1) t i b - 6 1 ( c t / t u o y r r a c o t k c o l c 4 . 3 1 1 . 5 1s n t u s h c i c 7 8 1k c o l c o t p u t e s d l o h t n u o c / n i y r r a c6 . 7 9 . 1 1 s n t h h c i c 8 8 1k c o l c o t d l o h d l o h t n u o c / n i y r r a c0 0 s n t o c h c i c 9 8 1c t / t u o y r r a c o t d l o h t n u o c / n i y r r a c s n h t a p c i r e n e g t o i m c r 0 9 1o i m o t t u o r e t n u o c / . g e r r o f d e d d a y a l e d 1 2s n f p r g c r 1 9 1p r g o t t u o r e t n u o c / . g e r r o f d e d d a y a l e d 1 2s n t c r o i m 2 9 1r e t n u o c / . g e r o t o i m r o f d e d d a y a l e d 4 5s n t c r p r g 3 9 1r e t n u o c / . g e r o t p r g r o f d e d d a y a l e d 4 5s n
specifications isplsi 6192 51 isplsi 6192 timing model glb reg delay i/o pin (output) orp delay feedback 4 pt bypass 20 pt xor delays control pts memory module register/ counter module input register i/o pin (input) y0,1,2 y3 d q grp glb reg bypass orp bypass dq rst re oe ck i/o reg bypass i/o cell orp glb grp i/o cell #25 - 29 #30 #31 #32 - 34 #40 - 42 #49 #192 #83 - 110 #140 - 156 #177 - 189 #113, 159 #114, 160, 193 #43 #44 reset y4 #24 #50 rst #51 #51 #35 #36 - 39 #47, 48 #45, 46 goe0,1 toe moe* 0902/6192 module pin module pin #112, 158, 191 #111, 157, 190 * = dedicated module output enable
specifications isplsi 6192 52 figure 51. typical device power consumption vs fmax power consumption power consumption in the isplsi 6192 device depends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 51 shows the relationship between power and operating speed. 100 150 200 0 10203040506070 f max (mhz) i cc (ma) notes: typical current at 5v, 25 c isplsi 6192 0127a/6192
specifications isplsi 6192 53 pin description: programmable logic module input - dedicated clock pins - these clock inputs are connected to one of the clock inputs of all the i/o cells in the device. input - dedicated clock pins - these clock inputs are connected to one of the clock inputs of all the glbs on the device. input - active low global reset pin which resets all of the glb and i/o registers in the device. input - this pin performs two functions. when ispen is low, this is the serial data in pin to load programming data into the device. when ispen is high, this pin is used as the test data in for the boundary scan operation input - this pin performs two functions. when ispen is low, this is the serial clock input pin for device programming. when ispen is high, this is the test clock pin used for the boundary scan operation. input/output pins - these are the general purpose i/o pins used by the logic array. name table 2 - 0002/6192 mqfp pin numbers description 32, 38, 44, 51, 56, 63, 68, 83, 88, 95, 171, 177, 184, 190, 198, 204, 2, 8, 15, 20 33, 40, 45, 52, 58, 64, 69, 84, 89, 96, 172, 179, 186, 192, 199, 205, 4, 9, 16, 34, 41, 47, 53, 60, 65, 79, 85, 90, 97, 173, 181, 187, 193, 200, 206, 5, 10, 17, i/o 0 - i/o 4 i/o 5 - i/o 9 i/o 10 - i/o 14 i/o 15 - i/o 19 i/o 20 - i/o 24 i/o 25 - i/o 29 i/o 30 - i/o 34 i/o 35 - i/o 39 i/o 40 - i/o 44 i/o 45 - i/o 49 i/o 50 - i/o 54 i/o 55 - i/o 59 i/o 60 - i/o 64 i/o 65 - i/o 69 i/o 70 - i/o 74 i/o 75 - i/o 79 i/o 80 - i/o 84 i/o 85 - i/o 89 i/o 90 - i/o 94 i/o 95 36, 42, 48, 54, 61, 66, 80, 86, 92, 169, 175, 182, 188, 194, 201, 207, 6, 12, 18, 37, 43, 49, 55, 62, 67, 82, 87, 94, 170, 176, 183, 189, 196, 203, 1, 7, 14, 19, input - global output enable input pins. 75 and 73 goe0 and goe1 25 reset 22, 24, 78 y0, y1 and y2 77, 76 y3 and y4 26 ispen/bscan 2 27 sdi/tdi 2 28 sclk/tclk 2 29 mode/tms 2 71 trst/nc 1, 2 136 sdo/tdo 2 output - this pin performs two functions. when ispen is logic low, it is the serial data out pin used to read the isp data. when ispen is high it functions as test data out pin for the boundary scan operation. input - test reset, active low to reset the boundary scan state machine. input - this pin performs two functions. when ispen is low, this is the mode pin to control the isp state machine operations. when ispen is high, this is the test mode select input for the boundary scan operation. input - test output enable pin. toe tristates all i/o pins when a logic low is driven 72 toe ground (gnd) 11, 70, 128, 174 202, 23, 81, 141, 180, 208 35, 93, 152, 185, gnd 46, 104, 158, 191, 59, 116, 164, 197, vcc 13, 74, 145, 21, 91, 162, 31, 118 178, vcc 39, 126, 195 57, 137, input - boundary scan enable. dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the mode, sdi, sdo and sclk options become active. 1. nc pins are not to be connected to any active signal, vcc or gnd. 2. pins have dual function capability.
specifications isplsi 6192 54 pin description: register/counter module input pin - active low enable pin used to write data from di/o(rc) pins to selected bank of register/counter. output pins - terminal count (timers) or carry out (counters) outputs. used only in timer or counter modes for register/counter module. input pin - serial data input to bit 15 of bank 0. used only in shift register configuration. input/output pins - these are the external data pins used by the register/counter module. they are tristated when the oe (rc) pin is inactive (high). they can be used as general-purpose logic inputs if the register/counter module does not use the external data interface. name table 2 - 0002/6192 reg/ctr mqfp pin numbers description 139, 146, 151, 159 140, 147, 153, 142, 148, 154, di/o 0 - di/o 4 (rc) di/o 5 - di/o 9 (rc) di/o 10 - di/o 14 (rc) di/o 15 (rc) 143, 149, 156, 166, 167, 168, 144, 150, 157, 165, tc/co0 - tc/co3 163 enable 160 sin 161 sout 138 oe (rc) input pin - register/counter output enable pin. enables the di/o(rc) pins when active low. output pin - serial data output from bit 0 of bank 7. used only in shift register configurations. name table 2 - 0002/6192ff mqfp pin numbers description 113, 120, 125, 132, 114, 121, 127, 133, 115, 122, 129, 134 di/o 0 - di/o 4 (fifo) di/o 5 - di/o 9 (fifo) di/o 10 - di/o 14 (fifo) di/o 15 - di/o 17 (fifo) 117, 123, 130, 119, 124, 131, 99 rst 110 rd or wr 101 ff 100 ef 103 alf 102 ale input pin - active low. this is a dual function pin. when data is read from the fifo to the external pins it acts as a read enable pin ( rd ) for port b to a configuration. when data is written to the fifo from the external pins it acts as a write control pin ( wr ) for port a to b configuration. when rd is low, data is read from the ram array sequentially. when wr is low, data is written to the ram array input pin - active low reset input used to reset the internal read and write pointers to the first location of the ram array. output pin - active low full flag pin to indicate that the fifo is full and further write operation is inhibited. output pin - active low empty flag pin to indicate the fifo is empty and further read operation is inhibited. input/output pins - these are the external data i/o pins used by the fifo. for the 512 x 9 fifo configuration, the higher 9 bits are used. these pins tristate when rd goes inactive (high). output pin - active low almost empty flag. it can be programmed to activate at any location. it has to be below the almost full flag. can be used as a general-purpose logic input if not used for external fifo interfacing. output pin - active low almost full flag. it can be programmed to activate at any location. can be used as a general-purpose logic input if not used for external fifo interfacing. pin description: fifo module
specifications isplsi 6192 55 pin description: dual port and single port ram module name table 2 - 0002/6192dp/sp mqfp pin numbers description 113, 120, 125, 132, 114, 121, 127, 133, 115, 122, 129, 134 di/o 0 - di/o 4 (ram) di/o 5 - di/o 9 (ram) di/o 10 - di/o 14 (ram) di/o 15 - di/o 17 (ram) 117, 123, 130, 119, 124, 131, 109 a8/rwh input pin - used as read/write control line for upper byte ram when in byte write mode. the ram performs a read operation when rwh is high and write operation when rwh is low. used as 9th address bit when ram is configured as 512x9. can be used as a general-pupose logic input if not needed for external ram interfacing. 110 rwl input pin - controls the read/write operation of the memory module. when operating in the byte write mode, rwl controls the read/write of the lower order byte while rwh controls the read/write operation of the higher order byte. 111 cs input pin - chip select. must be active low to perform read or write from external ram interface. can be used as a general-pupose logic input if not needed for external ram interfacing. 112 oe input pin - ram output enable. controls di/o(ram) pin tristating. pins tristate when oe is inactive (high). outputs enabled when oe active (low). 98 busya (dual port ram only) output pin - active low busy pin indicating that port a has lost the arbitration when both port a and port b are attempting to access the same ram location simultaneously. input/output pins - these are the data i/o pins used by the ram. for the 512x9 ram configuration, the high order 9 bits are used. these pins tristate when oe (ram) or cs (ram) goes inactive. in addition, if the rwh and/or rwl pin are in the write state (low), the appropriate byte(s) of di/o will tristate. di/o 0-8 can also be used for general- purpose logic inputs if not needed for ram interfacing from the i/o cellls (single port ram only). 99, 103, 100, 105, 101, 106, a0 - a3 a4 - a7 102, 108 input pins - address inputs to access locations in the ram array. a3 - a7 can also be used as general-purpose logic inputs if not needed for ram interfacing from the i/o cells.
specifications isplsi 6192 56 pin configuration: isplsi 6192ff isplsi 6192ff 208-pin mqfp pinout diagram isplsi 6192ff top view 208-mqfp/6192ff 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 i/o 79 i/o 80 1 nc i/o 81 i/o 82 i/o 83 i/o 84 i/o 85 i/o 86 i/o 87 gnd i/o 88 vcc i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 vcc y0 gnd y1 reset 2 ispen /bscan 2 sdi/tdi 2 sclk/tclk 2 mode/tms nc vcc i/o 0 i/o 1 i/o 2 gnd i/o 3 i/o 4 i/o 5 vcc i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 gnd i/o 12 i/o 13 i/o 14 1 nc i/o 15 i/o 16 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 i/o 17 i/o 18 i/o 19 i/o 20 vcc i/o 21 gnd i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 gnd 1, 2 trst /nc toe goe1 vcc goe0 y4 y3 y2 i/o 32 i/o 33 gnd i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 vcc i/o 43 gnd i/o 44 i/o 45 i/o 46 i/o 47 1 nc rst ef ff ale alf gnd 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 dio 13 (rc) nc 1 dio 12 (rc) dio 11 (rc) gnd dio 10 (rc) dio 9 (rc) dio 8 (rc) dio 7 (rc) dio 6 (rc) dio 5 (rc) vcc dio 4 (rc) dio 3 (rc) dio 2 (rc) gnd dio 1 (rc) dio 0 (rc) oe (rc) vcc tdo/sdo 2 nc 1 dio 17 (fifo) dio 16 (fifo) dio 15 (fifo) dio 14 (fifo) dio 13 (fifo) dio 12 (fifo) gnd dio 11 (fifo) vcc dio 10 (fifo) dio 9 (fifo) dio 8 (fifo) dio 7 (fifo) dio 6 (fifo) dio 5 (fifo) dio 4 (fifo) vcc dio 3 (fifo) gnd dio 2 (fifo) dio 1 (fifo) dio 0 (fifo) oe (fifo) nc 1 rd or wr (fifo) nc 1 nc 1 nc 1 nc 1 nc 1 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 gnd i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 gnd i/o 73 i/o 72 i/o 71 i/o 70 gnd i/o 69 vcc i/o 68 i/o 67 i/o 66 gnd i/o 65 i/o 64 i/o 63 i/o 62 i/o 61 gnd i/o 60 i/o 59 i/o 58 i/o 57 gnd i/o 56 vcc i/o 55 i/o 54 i/o 53 gnd i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 tc/co (3) (rc) tc/co (2) (rc) tc/co (1) (rc) tc/co (0) (rc) gnd enable (rc) vcc sout (rc) sin (rc) dio 15 (rc) gnd dio 14 (rc) 1. nc pins are not to be connected to any active signal, vcc or gnd. 2. pins have dual function capability.
specifications isplsi 6192 57 pin configuration: isplsi 6192dm isplsi 6192dm 208-pin mqfp pinout diagram isplsi 6192dm top view 208-mqfp/6192dm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 i/o 79 i/o 80 1 nc i/o 81 i/o 82 i/o 83 i/o 84 i/o 85 i/o 86 i/o 87 gnd i/o 88 vcc i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 vcc y0 gnd y1 reset 2 ispen /bscan 2 sdi/tdi 2 sclk/tclk 2 mode/tms 1 nc vcc i/o 0 i/o 1 i/o 2 gnd i/o 3 i/o 4 i/o 5 vcc i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 gnd i/o 12 i/o 13 i/o 14 1 nc i/o 15 i/o 16 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 i/o 17 i/o 18 i/o 19 i/o 20 vcc i/o 21 gnd i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 gnd 2 trst /nc toe goe1 vcc goe0 y4 y3 y2 i/o 32 i/o 33 gnd i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 vcc i/o 43 gnd i/o 44 i/o 45 i/o 46 i/o 47 busya (ram) a0 (ram) a1 (ram) a2 (ram) a3 (ram) a4 (ram) gnd 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 dio 13 (rc) nc 1 dio 12 (rc) dio 11 (rc) gnd dio 10 (rc) dio 9 (rc) dio 8 (rc) dio 7 (rc) dio 6 (rc) dio 5 (rc) vcc dio 4 (rc) dio 3 (rc) dio 2 (rc) gnd dio 1 (rc) dio 0 (rc) oe (rc) vcc sdo/tdo 2 nc dio 17 (ram) dio 16 (ram) dio 15 (ram) dio 14 (ram) dio 13 (ram) dio 12 (ram) gnd dio 11 (ram) vcc dio 10 (ram) dio 9 (ram) dio 8 (ram) dio 7 (ram) dio 6 (ram) dio 5 (ram) dio 4 (ram) vcc dio 3 (ram) gnd dio 2 (ram) dio 1 (ram) dio 0 (ram) oe (ram) cs (ram) rwl (ram) a8/rwh (ram) a7 (ram) nc 1 a6 (ram) a5 (ram) 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 gnd i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 gnd i/o 73 i/o 72 i/o 71 i/o 70 gnd i/o 69 vcc i/o 68 i/o 67 i/o 66 gnd i/o 65 i/o 64 i/o 63 i/o 62 i/o 61 gnd i/o 60 i/o 59 i/o 58 i/o 57 gnd i/o 56 vcc i/o 55 i/o 54 i/o 53 gnd i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 tc/co (3) (rc) tc/co (2) (rc) tc/co (1) (rc) tc/co (0) (rc) gnd enable (rc) vcc sout (rc) sin (rc) dio 15 (rc) gnd dio 14 (rc) 1. nc pins are not to be connected to any active signal, vcc or gnd. 2. pins have dual function capability.
specifications isplsi 6192 58 pin configuration: isplsi 6192sm isplsi 6192sm 208-pin mqfp pinout diagram isplsi 6192sm top view 208-mqfp/6192sm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 i/o 79 i/o 80 1 nc i/o 81 i/o 82 i/o 83 i/o 84 i/o 85 i/o 86 i/o 87 gnd i/o 88 vcc i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 vcc y0 gnd y1 reset 2 ispen /bscan 2 sdi/tdi 2 sclk/tclk 2 mode/tms 1 nc vcc i/o 0 i/o 1 i/o 2 gnd i/o 3 i/o 4 i/o 5 vcc i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 gnd i/o 12 i/o 13 i/o 14 1 nc i/o 15 i/o 16 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 i/o 17 i/o 18 i/o 19 i/o 20 vcc i/o 21 gnd i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 gnd 2 trst /nc toe goe1 vcc goe0 y4 y3 y2 i/o 32 i/o 33 gnd i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 vcc i/o 43 gnd i/o 44 i/o 45 i/o 46 i/o 47 1 nc a0 (ram) a1 (ram) a2 (ram) a3 (ram) a4 (ram) gnd 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 dio 13 (rc) nc 1 dio 12 (rc) dio 11 (rc) gnd dio 10 (rc) dio 9 (rc) dio 8 (rc) dio 7 (rc) dio 6 (rc) dio 5 (rc) vcc dio 4 (rc) dio 3 (rc) dio 2 (rc) gnd dio 1 (rc) dio 0 (rc) oe (rc) vcc tdo/sdo 2 nc 1 dio 17 (ram) dio 16 (ram) dio 15 (ram) dio 14 (ram) dio 13 (ram) dio 12 (ram) gnd dio 11 (ram) vcc dio 10 (ram) dio 9 (ram) dio 8 (ram) dio 7 (ram) dio 6 (ram) dio 5 (ram) dio 4 (ram) vcc dio 3 (ram) gnd dio 2 (ram) dio 1 (ram) dio 0 (ram) oe (ram) cs (ram) rwl (ram) a8/rwh (ram) a7 (ram) nc 1 a6 (ram) a5 (ram) 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 gnd i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 gnd i/o 73 i/o 72 i/o 71 i/o 70 gnd i/o 69 vcc i/o 68 i/o 67 i/o 66 gnd i/o 65 i/o 64 i/o 63 i/o 62 i/o 61 gnd i/o 60 i/o 59 i/o 58 i/o 57 gnd i/o 56 vcc i/o 55 i/o 54 i/o 53 gnd i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 tc/co (3) (rc) tc/co (2) (rc) tc/co (1) (rc) tc/co (0) (rc) gnd enable (rc) vcc sout (rc) sin (rc) dio 15 (rc) gnd dio 14 (rc) 1. nc pins are not to be connected to any active signal, vcc or gnd. 2. pins have dual function capability.
specifications isplsi 6192 59 part number description device number grade blank = commercial isplsi 6192 xx x x x power l = low package m = mqfp device family 0212/6192 xx speed 70 = 77 mhz f max 50 = 57 mhz f max ram module type ff = fifo sm = single port ram dm = dual port ram ordering information ram module f max t pd ordering number package fifo 77 15 isplsi 6192ff-70lm 208-pin mqfp 57 20 isplsi 6192ff-50lm 208-pin mqfp single port ram 77 15 isplsi 6192sm-70lm 208-pin mqfp 57 20 isplsi 6192sm-50lm 208-pin mqfp dual port ram 77 15 isplsi 6192dm-70lm 208-pin mqfp 57 20 isplsi 6192dm-50lm 208-pin mqfp

▲Up To Search▲

Price & Availability of ISPLSI6192SM-70LM

	To Download ISPLSI6192SM-70LM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .